From WikiChip
Editing Talk:arm/armv1
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page is not enabled for semantic in-text annotations due to namespace restrictions. Details about how to enable the namespace can be found on the configuration help page.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
− | |||
− | |||
==Corrections needed with the address space== | ==Corrections needed with the address space== | ||
x86 is exceptional in that it doesn't really care about alignment, not just of instructions (they're variable length, it has no choice) but of data. Many RISC architectures would work with units of 4 bytes, as such they only needed 30 bit addresses. I've seen some archs that have instructions for load the high 2 bytes, load the low 2 bytes of a 4 byte range. | x86 is exceptional in that it doesn't really care about alignment, not just of instructions (they're variable length, it has no choice) but of data. Many RISC architectures would work with units of 4 bytes, as such they only needed 30 bit addresses. I've seen some archs that have instructions for load the high 2 bytes, load the low 2 bytes of a 4 byte range. | ||
Anyway when considering how much memory it can address it probably should be 2^28, not 2^26, so that's 256 mb not 64 mb - that or it has a 24 bit program counter. [[User:Alec|Alec]] ([[User talk:Alec|talk]]) 13:22, 27 June 2017 (EDT) | Anyway when considering how much memory it can address it probably should be 2^28, not 2^26, so that's 256 mb not 64 mb - that or it has a 24 bit program counter. [[User:Alec|Alec]] ([[User talk:Alec|talk]]) 13:22, 27 June 2017 (EDT) | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− |