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{{lithography processes}} | {{lithography processes}} | ||
− | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. | + | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of [[integrated circuit]]s using a 7 nm process has begun in 2018. This technology will be replaced by the [[5 nm lithography process|5 nm process]] around 2020/21. |
− | + | == Industry == | |
+ | Only three semiconductor foundries are currently working on a 7nm process: [[Intel]], [[Samsung]] and [[TSMC]]. | ||
− | + | {{future information}} | |
− | |||
− | |||
− | |||
− | + | {{finfet nodes comp | |
+ | <!-- Intel --> | ||
+ | | process 1 fab = [[Intel]] | ||
+ | | process 1 name = P1276 (CPU), P1277 (SoC) | ||
+ | | process 1 date = | ||
+ | | process 1 lith = EUV | ||
+ | | process 1 immersion = | ||
+ | | process 1 exposure = | ||
+ | | process 1 wafer type = Bulk | ||
+ | | process 1 wafer size = 300 mm | ||
+ | | process 1 transistor = | ||
+ | | process 1 volt = | ||
+ | | process 1 delta from = [[10 nm]] Δ | ||
+ | | process 1 fin pitch = | ||
+ | | process 1 fin pitch Δ = | ||
+ | | process 1 fin width = | ||
+ | | process 1 fin width Δ = | ||
+ | | process 1 fin height = | ||
+ | | process 1 fin height Δ = | ||
+ | | process 1 gate len = | ||
+ | | process 1 gate len Δ = | ||
+ | | process 1 cpp = | ||
+ | | process 1 cpp Δ = | ||
+ | | process 1 mmp = | ||
+ | | process 1 mmp Δ = | ||
+ | | process 1 sram hp = | ||
+ | | process 1 sram hp Δ = | ||
+ | | process 1 sram hd = | ||
+ | | process 1 sram hd Δ = | ||
+ | | process 1 sram lv = | ||
+ | | process 1 sram lv Δ = | ||
+ | | process 1 dram = | ||
+ | | process 1 dram Δ = | ||
+ | <!-- TSMC --> | ||
+ | | process 2 fab = [[TSMC]] | ||
+ | | process 2 name = 7FF, 7FF+<info>will use EUVL instead of immersion lithography</info>, 7HPC | ||
+ | | process 2 date = Q1, 2018 | ||
+ | | process 2 lith = 193 nm | ||
+ | | process 2 immersion = Yes | ||
+ | | process 2 exposure = SAQP | ||
+ | | process 2 wafer type = Bulk | ||
+ | | process 2 wafer size = 300 mm | ||
+ | | process 2 transistor = FinFET | ||
+ | | process 2 volt = 0.70 V | ||
+ | | process 2 delta from = [[10 nm]] Δ | ||
+ | | process 2 fin pitch = | ||
+ | | process 2 fin pitch Δ = | ||
+ | | process 2 fin width = | ||
+ | | process 2 fin width Δ = | ||
+ | | process 2 fin height = | ||
+ | | process 2 fin height Δ = | ||
+ | | process 2 gate len = | ||
+ | | process 2 gate len Δ = | ||
+ | | process 2 cpp = 54 nm | ||
+ | | process 2 cpp Δ = 0.84x | ||
+ | | process 2 mmp = 40 nm | ||
+ | | process 2 mmp Δ = 0.95x | ||
+ | | process 2 sram hp = | ||
+ | | process 2 sram hp Δ = | ||
+ | | process 2 sram hd = 0.027 µm² | ||
+ | | process 2 sram hd Δ = 0.64x | ||
+ | | process 2 sram lv = | ||
+ | | process 2 sram lv Δ = | ||
+ | | process 2 dram = | ||
+ | | process 2 dram Δ = | ||
+ | <!-- GlobalFoundries --> | ||
+ | | process 3 fab = [[GlobalFoundries]] | ||
+ | | process 3 name = 7LP<info>7nm Leading Performance</info> | ||
+ | | process 3 date = cancelled | ||
+ | | process 3 lith = 193 nm | ||
+ | | process 3 immersion = Yes | ||
+ | | process 3 exposure = SAQP | ||
+ | | process 3 wafer type = Bulk | ||
+ | | process 3 wafer size = 300 mm | ||
+ | | process 3 transistor = FinFET | ||
+ | | process 3 volt = 0.70 V | ||
+ | | process 3 delta from = [[14 nm]] Δ | ||
+ | | process 3 fin pitch = 30 nm | ||
+ | | process 3 fin pitch Δ = 0.63x | ||
+ | | process 3 fin width = | ||
+ | | process 3 fin width Δ = | ||
+ | | process 3 fin height = | ||
+ | | process 3 fin height Δ = | ||
+ | | process 3 gate len = | ||
+ | | process 3 gate len Δ = | ||
+ | | process 3 cpp = 56 nm | ||
+ | | process 3 cpp Δ = 0.72x | ||
+ | | process 3 mmp = 40 nm | ||
+ | | process 3 mmp Δ = 0.63x | ||
+ | | process 3 sram hp = 0.0353 µm² | ||
+ | | process 3 sram hp Δ = 0.44x | ||
+ | | process 3 sram hd = 0.0269 µm² | ||
+ | | process 3 sram hd Δ = 0.42x | ||
+ | | process 3 sram lv = | ||
+ | | process 3 sram lv Δ = | ||
+ | | process 3 dram = | ||
+ | | process 3 dram Δ = | ||
+ | <!-- Samsung --> | ||
+ | | process 4 fab = [[Samsung]] | ||
+ | | process 4 name = 7LPE<info>7 nm Low Power Early</info> | ||
+ | | process 4 date = 2019 | ||
+ | | process 4 lith = EUV | ||
+ | | process 4 immersion = | ||
+ | | process 4 exposure = SE | ||
+ | | process 4 wafer type = Bulk | ||
+ | | process 4 wafer size = 300 mm | ||
+ | | process 4 transistor = FinFET | ||
+ | | process 4 volt = | ||
+ | | process 4 delta from = [[10 nm]] Δ | ||
+ | | process 4 fin pitch = | ||
+ | | process 4 fin pitch Δ = | ||
+ | | process 4 fin width = | ||
+ | | process 4 fin width Δ = | ||
+ | | process 4 fin height = | ||
+ | | process 4 fin height Δ = | ||
+ | | process 4 gate len = | ||
+ | | process 4 gate len Δ = | ||
+ | | process 4 cpp = 54 nm | ||
+ | | process 4 cpp Δ = 0.79x | ||
+ | | process 4 mmp = 36 nm | ||
+ | | process 4 mmp Δ = 0.7x | ||
+ | | process 4 sram hp = | ||
+ | | process 4 sram hp Δ = | ||
+ | | process 4 sram hd = 0.0260 µm² | ||
+ | | process 4 sram hd Δ = 0.65x | ||
+ | | process 4 sram lv = | ||
+ | | process 4 sram lv Δ = | ||
+ | | process 4 dram = | ||
+ | | process 4 dram Δ = | ||
+ | <!-- Common Platform --> | ||
+ | | process 5 fab = Common Platform<info>[[IBM]], [[Samsung]], [[GlobalFoundries]]</info> Paper | ||
+ | | process 5 name = | ||
+ | | process 5 date = | ||
+ | | process 5 lith = EUV | ||
+ | | process 5 immersion = | ||
+ | | process 5 exposure = SE | ||
+ | | process 5 wafer type = Bulk | ||
+ | | process 5 wafer size = 300 mm | ||
+ | | process 5 transistor = FinFet | ||
+ | | process 5 volt = | ||
+ | | process 5 delta from = [[10 nm]] Δ | ||
+ | | process 5 fin pitch = | ||
+ | | process 5 fin pitch Δ = | ||
+ | | process 5 fin width = | ||
+ | | process 5 fin width Δ = | ||
+ | | process 5 fin height = | ||
+ | | process 5 fin height Δ = | ||
+ | | process 5 gate len = | ||
+ | | process 5 gate len Δ = | ||
+ | | process 5 cpp = 48 nm | ||
+ | | process 5 cpp Δ = 0.75x | ||
+ | | process 5 mmp = 36 nm | ||
+ | | process 5 mmp Δ = 0.75x | ||
+ | | process 5 sram hp = | ||
+ | | process 5 sram hp Δ = | ||
+ | | process 5 sram hd = | ||
+ | | process 5 sram hd Δ = | ||
+ | | process 5 sram lv = | ||
+ | | process 5 sram lv Δ = | ||
+ | | process 5 dram = | ||
+ | | process 5 dram Δ = | ||
+ | }} | ||
− | == | + | === Intel === |
− | + | * '''Note:''' For the most part, foundries' 7nm process is competing against [[10_nm_lithography_process#Intel|Intel's 10nm process]], not their 7nm. | |
+ | |||
+ | On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017 Mark Bohr, Intel's Senior Fellow and Director of Process Architecture and Integration, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the [[5 nm]] and [[3 nm]] nodes. Details of their 7 nm node have not been disclosed yet. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June. | ||
− | + | === GlobalFoundries === | |
+ | * '''Note:''' As of august 2018 GlobalFoundries has announced they will suspend further development of their 7nm, 5nm and 3nm process. | ||
+ | [[File:globalfoundries interconnect 7nm.jpg|right|350px]] | ||
+ | On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready. | ||
− | + | The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips. | |
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=== TSMC === | === TSMC === | ||
− | + | [[File:7nm tsmc.jpeg|right|200px]] | |
+ | In ISSCC 2017, the memory group at [[TSMC]] detailed their test 256 Mib SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using SAQP. The over die is 0.34x the size of their [[16 nm process]] version. TSMC's 7nm process density is 1.6X compared to their 10nm process. Minimum metal pitch is 40 nm, as reported at IEDM 2016. TSMC claims their 7nm process will deliver a 20% performance improvement and a 40% reduction in power consumption. | ||
− | + | The 7nm node will come in two variants, one optimized for mobile applications and a second one optimized for High performance applications. | |
− | + | TSMC plans to introduce a second improved process called 7nm+ a year later, which will introduce some layers processed with EUVL. This will improve yields and reduce fab cycle times. The 7nm+ process will deliver improved power consumption and between 15-20% area scaling over their first generation 7nm process. | |
− | TSMC | ||
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|- | |- | ||
− | | | + | ! colspan="2" | TSMC 256 Mib SRAM demo 7 nm wafer |
|- | |- | ||
− | | | + | | |
− | + | <table class="wikitable"> | |
− | + | <tr><th>Technology</th><td>7 nm HK-MG FinFET</td></tr> | |
− | + | <tr><th>Metal scheme</th><td>1 Poly / 7 Metal</td></tr> | |
− | + | <tr><th>Supply voltage</th><td>0.75 V (core)<br>1.8 V (i/o)</td></tr> | |
− | + | <tr><th>Bit cell size</th><td>0.027 µm²</td></tr> | |
− | + | <tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr> | |
− | + | <tr><th>Capacity</th><td>256 Mib</td></tr> | |
− | + | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr> | |
− | + | <tr><th>Die Size</th><td>5903 µm x 7223 µm = 42.64 mm²</td></tr> | |
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</table> | </table> | ||
− | + | | [[File:tsmc 7nm SRAM block.png]] | |
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− | + | === Samsung=== | |
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− | === Samsung === | ||
Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development. | Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development. | ||
On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size. | On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size. | ||
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== 7 nm Microprocessors== | == 7 nm Microprocessors== | ||
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** {{pezy|PEZY-SC3}} | ** {{pezy|PEZY-SC3}} | ||
* MediaTek | * MediaTek | ||
− | ** {{mediatek | + | ** {{mediatek|Helio M70}} |
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* Apple | * Apple | ||
** {{apple|A12}} | ** {{apple|A12}} | ||
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* HiSilicon (Huawei) | * HiSilicon (Huawei) | ||
− | ** {{ | + | ** {{Kirin 980}} |
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{{expand list}} | {{expand list}} | ||
== 7 nm Microarchitectures== | == 7 nm Microarchitectures== | ||
* AMD | * AMD | ||
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** {{amd|Navi|l=arch}} | ** {{amd|Navi|l=arch}} | ||
** {{amd|Zen 2|l=arch}} | ** {{amd|Zen 2|l=arch}} | ||
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== See also == | == See also == | ||
− | |||
− | + | * {{intel|process|Intel proces technology history}} | |
− | * {{ | + | |
− | * | + | == References == |
− | * | + | * Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. |
− | * | + | * Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016. |
+ | * Samsung/GlobalFoundries, [[IEEE]] [[International Electron Devices Meeting]] (IEDM) 2016 | ||
+ | [[category:lithography]] |