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Editing 5 nm lithography process
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=== Intel === | === Intel === | ||
− | ==== | + | ==== P1278 ==== |
− | Intel | + | Intel's 5-nanometer process node is expected to ramp around the 2023 timeframe. |
=== TSMC === | === TSMC === | ||
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===== SRAM ===== | ===== SRAM ===== | ||
− | + | TWo [[6T]] [[SRAM]] [[bitcells]] were disclosed by TSMC. The high-performance cell is 0.025 µm² while the high-density cell is 0.021 µm². Assuming a ballpark assist circuit overhead of around 30%, the high-density cells yields an estimate of ~32 Mib/mm² of cache. This an increase of 30% from [[N7]] which is around 24.7 Mib/mm². At ISSCC 2020, TSMC presented a test shuttle with 135 Mib of HD SRAM and additional IPs. Their reported density for the HD cells is similar to our estimates. | |
{| class="wikitable collapsible collapsed tc1" | {| class="wikitable collapsible collapsed tc1" | ||
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| Metal 1 || 28 nm || 0.70x | | Metal 1 || 28 nm || 0.70x | ||
|- | |- | ||
− | | Metal 2 || 36 nm || | + | | Metal 2 || 36 nm || 0.75x |
|- | |- | ||
− | | Metal 3 || 32 nm || 0. | + | | Metal 3 || 32 nm || 0.88x |
|- | |- | ||
| Metal 4 || 44 nm || 1.0x | | Metal 4 || 44 nm || 1.0x | ||
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* Apple | * Apple | ||
**[[apple/ax/a14|A14 Bionic]] | **[[apple/ax/a14|A14 Bionic]] | ||
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**[[apple/mx/m1|M1]] | **[[apple/mx/m1|M1]] | ||
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{{expand list}} | {{expand list}} | ||