From WikiChip
Editing 5 nm lithography process
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{lithography processes}} | {{lithography processes}} | ||
− | The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin | + | The '''5 nanometer (5 nm or 50 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin sometimes around 2020. |
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | ||
Line 18: | Line 18: | ||
=== Intel === | === Intel === | ||
− | ==== | + | ==== P1278 ==== |
− | Intel | + | Intel's 5-nanometer process node is expected to ramp around the 2023 timeframe. |
=== TSMC === | === TSMC === | ||
− | |||
− | |||
==== N5 ==== | ==== N5 ==== | ||
− | TSMC started its [[risk production]] of the 5-nanometer, '''N5''', node in March 2019 | + | TSMC started its [[risk production]] of the 5-nanometer, '''N5''', node in March 2019 with production expected to start in the first quarter of 2020. |
− | |||
− | |||
− | [[ | + | N5 is planned as a [[full node]] successor to the company's [[N7 node]], featuring 1.8x improvement in logic density. The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, 5 nm makes extensive use of [[EUV]] for more critical layers in order to reduce the [[multi-patterning]] complexity. |
− | |||
{| class="wikitable" style="text-align: center;" | {| class="wikitable" style="text-align: center;" | ||
|- | |- | ||
− | ! colspan="3" | N5 | + | ! colspan="3" | N5 PPA vs. [[N7]] |
|- | |- | ||
− | ! Speed @ | + | ! Speed @ iso-power !! Power @ iso-speed !! Max speed improvement<br>@ Vdd (eLVT) |
|- | |- | ||
| ~15% || ~30% || ~25% | | ~15% || ~30% || ~25% | ||
|} | |} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | + | The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. For N5, TSMC is also offering an eLVT library that offers 25% high speed at Vdd. N5 targets both low-power mobile and high-performance compute with this node. In addition to a target density improvement of ~1.8x, TSMC has also improved the analog circuit density by ~1.2x. | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
==== N5P ==== | ==== N5P ==== | ||
− | As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called '''N5 Performance-enhanced version''' ('''N5P'''). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at | + | As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called '''N5 Performance-enhanced version''' ('''N5P'''). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021. |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Samsung === | === Samsung === | ||
Line 93: | Line 47: | ||
{| class="wikitable" style="text-align: center;" | {| class="wikitable" style="text-align: center;" | ||
|- | |- | ||
− | ! colspan="3" | 5LPE | + | ! colspan="3" | 5LPE PPA vs. [[7LPP]] |
|- | |- | ||
! Speed @ iso-power !! Power @ iso-speed | ! Speed @ iso-power !! Power @ iso-speed | ||
Line 165: | Line 119: | ||
| Metal 1 || 28 nm || 0.70x | | Metal 1 || 28 nm || 0.70x | ||
|- | |- | ||
− | | Metal 2 || 36 nm || | + | | Metal 2 || 36 nm || 0.75x |
|- | |- | ||
− | | Metal 3 || 32 nm || 0. | + | | Metal 3 || 32 nm || 0.88x |
|- | |- | ||
| Metal 4 || 44 nm || 1.0x | | Metal 4 || 44 nm || 1.0x | ||
Line 175: | Line 129: | ||
* PEZY | * PEZY | ||
** {{pezy|PEZY-SC4}} | ** {{pezy|PEZY-SC4}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
{{expand list}} | {{expand list}} | ||
Line 227: | Line 142: | ||
* Samsung, Arm TechCon, 2019 | * Samsung, Arm TechCon, 2019 | ||
* TSMC, Arm TechCon, 2019 | * TSMC, Arm TechCon, 2019 | ||
− | |||
[[category:lithography]] | [[category:lithography]] |