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| {{lithography processes}} | | {{lithography processes}} |
− | The '''16 nanometer (16 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[20 nm lithography process|20 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with [[10 nm lithography process|10 nm process]] in 2017. | + | The '''16 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[20 nm lithography process|20 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 16 nm process began in 2014. This technology is set to replaced by [[14 nm lithography process|14 nm process]] (HN) (2014) and [[10 nm lithography process|10 nm process]] (FN) in 2017. |
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− | == Industry == | + | == 16 nm Microprocessors== |
− | An enhanced version of TSMC's 16nm process was introduced in late 2016 called "12nm".
| + | {{expand list}} |
− | {{finfet nodes comp | |
− | <!-- Intel -->
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− | | process 1 fab = [[TSMC]]
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− | | process 1 name = 16FF<info>16nm FinFET</info>, 16FF+<info>16nm FinFET Plus</info>, 16FFC, 12FFC<info>12nm FinFET Compact</info>, 12FFN
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− | | process 1 date = 3Q 2015
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− | | process 1 lith = 193 nm
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− | | process 1 immersion = Yes
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− | | process 1 exposure =
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− | | process 1 wafer type = Bulk
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− | | process 1 wafer size = 300 mm
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− | | process 1 transistor = FinFET
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− | | process 1 volt = 0.75 V
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− | | process 1 delta from = [[20 nm]] Δ
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− | | process 1 fin pitch = 48 nm
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− | | process 1 fin pitch Δ = -
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− | | process 1 fin width =
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− | | process 1 fin width Δ =
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− | | process 1 fin height = 37 nm
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− | | process 1 fin height Δ =
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− | | process 1 gate len = 34 nm
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− | | process 1 gate len Δ =
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− | | process 1 cpp = 90 nm
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− | | process 1 cpp Δ = 1x
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− | | process 1 mmp = 64 nm
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− | | process 1 mmp Δ = 1x
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− | | process 1 sram hp =
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− | | process 1 sram hp Δ =
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− | | process 1 sram hd = 0.074 µm²
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− | | process 1 sram hd Δ = 0.86x
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− | | process 1 sram lv =
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− | | process 1 sram lv Δ =
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− | | process 1 dram =
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− | | process 1 dram Δ =
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− | }} | |
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− | === TSMC ===
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− | [[File:tsmc 16nm.jpg|right|300px]]
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− | TSMC uses the same [[BEOL]] as its 20nm process. They named their process 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly 10-15% performance improvement. A final 16FFC (16FF Compact) designed to reduce cost through less masks while using half the power.
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− | In late 2016 TSMC announced a "12nm" process (e.g. 12FFC<info>12nm FinFET Compact Technology</info>) which uses the similar design rules as the 16nm node but a tighter metal pitch, providing a slight density improvement. The enhanced process is said to feature lower leakage better and cost characteristics and perhaps a better name (vs. "14nm"). 12nm is expected to enter mass production in late 2017.
| + | == 16 nm System on Chips== |
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− | {| class="collapsible collapsed wikitable"
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− | |-
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− | ! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer
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− | |-
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− | <table class="wikitable">
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− | <tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr>
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− | <tr><th>Metal scheme</th><td>1 Poly / 7 Metal</td></tr>
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− | <tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr>
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− | <tr><th>Bit cell size</th><td>0.07 µm²</td></tr>
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− | <tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr>
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− | <tr><th>Capacity</th><td>128 Mib</td></tr>
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− | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
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− | <tr><th>Die Size</th><td>42.6 mm²</td></tr>
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− | </table>
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− | | [[File:tsmc 16nm SRAM block.png|400px]]
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− | |}
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− | == 16 nm Microprocessors==
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− | * HiSilicon
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− | ** {{hisil|Kirin}}
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− | * MediaTek
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− | ** {{mediatek|Helio}}
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− | * Microsoft
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− | ** {{microsoft|Scorpio Engine}}
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− | * Nvidia
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− | ** {{nvidia|Drive Xavier}}
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− | ** {{nvidia|Pascal}}
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− | * PEZY
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− | ** {{pezy|PEZY-SC2}}
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− | * Renesas
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− | ** {{renesas|R-Car}}
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| {{expand list}} | | {{expand list}} |
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| == 16 nm Microarchitectures== | | == 16 nm Microarchitectures== |
− | * AppliedMicro/Ampere
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− | ** {{apm|Skylark|l=arch}}
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− | * ARM
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− | ** {{armh|Cortex-A55|l=arch}}
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− | * Phytium
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− | ** {{phytium|Mars II|l=arch}}
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− | * Zhaoxin
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− | ** {{zhaoxin|LuJiaZui|l=arch}}
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| {{expand list}} | | {{expand list}} |
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− | == References ==
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− | * Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
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− | * Wu, Shien-Yang, et al. "A 16nm FinFET CMOS technology for mobile SoC and computing applications." Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013.
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− | * TechInsights/Chipworks, Kevin Gibb, The ConFab 2016
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− | [[category:lithography]] | + | [[Category:Lithography]] |