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FrontEnd
L2 Cache256-512 KiB 8-Way
Unified STLB (1280-entry 5-Way)
To L3
Execution Engine
32B/cycle
2x 32B/cycle
EUs
Branch Predictor(BPU)
Rename / Allocate / CommitReOrder Buffer (160-entry)
L1 Instruction Cache64 KiB 4-Way
Instruction TLB(48-entry)
16 Bytes/cycle
Instruction Fetch
4-8 Instructions/cycle
Inst
Inst
Inst
MOP
Dispatch
General-PurposeRegister File
Advanced SIMD & FPRegister File
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
SystemRegisters
Integer
ASIMD
Data TLB(48-entry)
16B/cycle
16B/cycle
32B/cycle
L1 Data Cache64 KiB 4-Way
NanoBTB (64-entry)
MicroBTB (64-entry)
Main BTB (8K)
32B/cycle
ReturnStack
MSHR(20-entry)
MSHR(46-entry)
32B/cycle
MOP Cache(1.5K-entries)
Inst
Decode Queue(16 x 32b)
4-Way Decode
Decoder
Decoder
Decoder
Decoder
MOP
MOP
MOP
MOP
MOP
MOP
MOP
MOP
MOP
1-6 MOPs
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
Branch
µOP
Port
Issue
Port
ALU
µOP
Port
ALU
µOP
Port
ALU
µOP
MAC
DIV
Port
ALU
µOP
IMAC
FADD
FDIV
FMUL
Port
ALU
µOP
FADD
FMUL
Port
µOP
AGU
Port
µOP
AGU
Integer Issue Queue
Port
ALU
µOP
Branch
µOP
Port
FPU Issue Queue
Port
µOP
StoreData
Port
µOP
StoreData
LSU Issue Queue
LSU
Store Buffer(90-entry)
Load Buffer(85-entry)
1-4 MOPs