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Front End
ExecutionEngine
Memory
L2 Cache512KiB 8-Way
L3
DTLB
Load Buffer(72 entries)
32B/cycle
(44 entries)
Store Buffer
32B/cycle store
WCB
ITLB
OP CacheTags
L1 Instruction Cache64KiB 4-Way
32B/Cycle
32B/Cycle
PhysicalRequest Queue
L1/L2 BTBReturn Stack (32 entry) Indirect Target Array (ITA)(512 entry; direct map)
Next PC
Instruction Byte Buffer
PreDecode / Pick
OP Cache(2K entry)
6 µOPs
4-8 MOPs
4 Instructions
Integer
FP/SIMD
4-Way Decode(Including fused µOPs)
Decoder
Decoder
Decoder
Decoder
Dispatch
MicroCode ROM(MSROM)
Stack EngineMemfile
µOP Queue (72 entry)
4 µOPs
Rename / Allocate
Physical Register File (168 entries)
I Scheduler(14 entries)
I Scheduler(14 entries)
I Scheduler(14 entries)
I Scheduler(14 entries)
Mem Sche(14 entries)
Mem Sche(14 entries)
AGU0
AGU1
Forwarding Muxes
ALUBranch
ALUBranch
ALUIMUL
ALUIDIV
Non-Scheduling Queue (NSQ)
128 bitloads
LDCVT
128-bitFMAFMUL
128-bitFADD
128-bitFMAFMUL
128-bitFADD
Forwarding Muxes
Physical Register File (160 entries)
Scheduling Queue (SQ)(96 entries)
L1 Data Cache32KiB 8-Way
2x128-bit
2 loads/cycle
1 store/cycle
4-8 MOPs
Move Elimination
Rename / Allocate
Store to LoadForwarding
8 entry L0 (all sizes)64 entry L1 (all sizes)512 entry L2 (no 1G)
Retire Queue(192 entries)
8-wide retire
Branch Fusion
HashPerceptron
4 µOPs
6 µOPs
64 entry L11.5K entry L2 (no 1G)
Micro-Tags(L1$ & µOP$)