https://en.wikichip.org/w/api.php?action=feedcontributions&user=87.214.221.129&feedformat=atom
WikiChip - User contributions [en]
2024-03-28T13:08:30Z
User contributions
MediaWiki 1.28.1
https://en.wikichip.org/w/index.php?title=samsung/exynos_modem&diff=94161
samsung/exynos modem
2019-10-23T22:13:36Z
<p>87.214.221.129: /* 5G NR */ Added 5G Exynos Modem 5123</p>
<hr />
<div>{{samsung title|Exynos Modem}}<br />
Samsung's Exynos Modems are a series of mobile radio modems under the Exynos brand.<br />
<br />
== Products ==<br />
=== 5G NR ===<br />
==== Exynos Modem 5123 <ref>https://news.samsung.com/global/new-premium-mobile-processor-and-5g-modem-unveiled-at-samsung-tech-day Exynos modem 5123</ref> ====<br />
* 5G NR: Sub-6GHz, mmWave<br />
* Supported Modes: LTE-FDD, LTE-TDD, HSPA, TD-SCDMA, WCDMA, CDMA, GSM/EDGE<br />
* Downlink Features:<br />
** 8CA (Carrier Aggregation) in 5G NR<br />
** 8CA (Carrier Aggregation) in LTE<br />
** 4x4 MIMO<br />
** FD-MIMO<br />
** Up to 1024-QAM in sub-6GHz<br />
** Up to 64-QAM in mmWave<br />
* Uplink Features:<br />
** 2CA (Carrier Aggregation) in 5G NR<br />
** 2CA (Carrier Aggregation) in LTE<br />
** Up to 256-QAM in sub-6GHz<br />
** Up to 64-QAM in mmWave<br />
* Process: 7nm EUV FinFET Process<br />
<br />
==== Exynos Modem 5100 <ref>https://www.samsung.com/semiconductor/minisite/exynos/products/modemrf/exynos-modem-5100/ Exynos modem 5100</ref> ====<br />
* 5G NR: Sub-6GHz, mmWave<br />
* Supported Modes: LTE-FDD, LTE-TDD, HSPA, TD-SCDMA, WCDMA, CDMA, GSM/EDGE<br />
* Downlink Features:<br />
** 8CA (Carrier Aggregation) in 5G NR<br />
** 8CA (Carrier Aggregation) in LTE<br />
** 4x4 MIMO<br />
** FD-MIMO<br />
** Up to 256-QAM in sub-6GHz<br />
** Up to 64-QAM in mmWave<br />
* Uplink Features:<br />
** 2CA (Carrier Aggregation) in 5G NR<br />
** 2CA (Carrier Aggregation) in LTE<br />
** Up to 256-QAM in sub-6GHz<br />
** Up to 64-QAM in mmWave<br />
* Process: 10nm FinFET Process<br />
<br />
=== 4G LTE ===<br />
==== Exynos Modem 333 <ref>https://www.samsung.com/semiconductor/minisite/exynos/products/modemrf/exynos-modem-333/ Exynos Modem 333</ref>====<br />
* LTE Cat. 10<br />
* Downlink: 3CA 450Mbps 64-QAM<br />
* Uplink: 2CA 100Mbps 16-QAM<br />
* 28nm HKMG Process<br />
<br />
==== Exynos Modem 303 <ref>https://www.samsung.com/semiconductor/minisite/exynos/products/modemrf/exynos-modem-303/ Exynos Modem 303</ref>====<br />
* LTE Cat. 6<br />
* Downlink: 2CA 300Mbps 64-QAM<br />
* Uplink: 100Mbps 16-QAM<br />
* 28nm HKMG Process<br />
<br />
=== IoT ===<br />
==== Exynos i T200 <ref>https://www.samsung.com/semiconductor/minisite/exynos/products/iot/exynos-i-t200/ Exynos i T200</ref> ==== <br />
* CPU: Cortex®-R4 @ 320MHz, Cortex®-M0+ @ 320MHz<br />
* WiFi: 802.11b/g/n Single band (2.4GHz)<br />
* On-chip Memory: SRAM 1.4MB<br />
* Interface: SDIO/ I2C/ SPI/ UART/ PWM/ I2S<br />
* Front-end Module: Integrated T/R switch, Power Amplifier, Low Noise Amplifier<br />
* Security: WEP 64/128, WPA, WPA2, AES, TKIP, WAPI, PUF (Physically Unclonable Function)<br />
<br />
==== Exynos i S111 <ref>https://www.samsung.com/semiconductor/minisite/exynos/products/iot/exynos-i-s111/ Exynos i S111</ref> ====<br />
* CPU: Cortex®-M7 200MHz<br />
* Modem: LTE Release 14 NB-IoT<br />
** Downlink: 127 kb/s<br />
** Uplink: 158 kb/s<br />
* On-chip Memory: SRAM 512KB<br />
* Interface: USI, UART, I2C, GPIO, eSIM I/F, SDIO(Host), QSPI(Single/Dual/Quad IO mode), SMC<br />
* Security: eFuse, AES, SHA-2, PKA, Secure Storage, Security Sub-System, PUF<br />
* GNSS: GPS, Galileo, GLONASS, BeiDou<br />
<br />
== References ==</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a34&diff=93668
arm holdings/microarchitectures/cortex-a34
2019-09-24T10:42:16Z
<p>87.214.221.129: Add specifications table</p>
<hr />
<div>{{armh title|Cortex-A34|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Cortex-A34<br />
|designer=ARM Holdings<br />
|manufacturer=TSMC<br />
|stages=8<br />
|isa=ARMv8 AArch64<br />
|extension=NEON (optional)<br />
|extension 2=Cryptography (optional)<br />
|l1i=8k-64k<br />
|l1d=8k-64k<br />
|l2=128KB-1MB<br />
|predecessor=Cortex-A35<br />
|predecessor link=arm_holdings/microarchitectures/cortex-a35<br />
}}<br />
'''Cortex-A34''' is the successor to the {{\\|Cortex-A35}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.<br />
<br />
== Architecture ==<br />
<br />
=== Key changes from {{\\|Cortex-A5}} ===<br />
{{empty section}}<br />
<br />
== Specifications ==<br />
{| class="wikitable"<br />
|-<br />
| Architecture || 64-Bit Armv8-A (AArch64 only)<br />
|-<br />
| Pipeline || In order<br />
|-<br />
| L1 I-Cache / D-Cache || 8k-64k<br />
|-<br />
| L2 Cache || 128KB-1MB<br />
|-<br />
| Multicore || 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology<br />
|-<br />
| ISA Support || AArch64 for 64-bit support and new architectural features<br />TrustZone security technology<br />Neon Advanced SIMD<br />DSP and SIMD extensions<br />VFPv4 Floating point<br />Hardware virtualization support<br />
|-<br />
| Debug & Trace || CoreSight SoC-400<br />
|}</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=mediatek/helio/p65&diff=92129
mediatek/helio/p65
2019-06-25T21:38:11Z
<p>87.214.221.129: Created mediatek/helio/p65</p>
<hr />
<div>{{mediatek title|Helio P65}}<br />
{{chip<br />
|name=P65<br />
|no image=Yes<br />
|designer=MediaTek<br />
|designer 2=ARM Holdings<br />
|manufacturer=TSMC<br />
|model number=P65<br />
|market=Mobile<br />
|first announced=June 25, 2019<br />
|first launched=June 25, 2019<br />
|family=Helio<br />
|series=Helio P<br />
|frequency=2,000 MHz<br />
|frequency 2=2,000 MHz<br />
|isa=ARMv8<br />
|isa family=ARM<br />
|microarch=Cortex-A75<br />
|microarch 2=Cortex-A55<br />
|core name=Cortex-A75<br />
|core name 2=Cortex-A55<br />
|process=12 nm<br />
|technology=CMOS<br />
|word size=64 bit<br />
|core count=8<br />
|thread count=8<br />
|max cpus=1<br />
|max memory=8 GiB<br />
}}<br />
'''Helio P65''' ('''MT????''') is a {{arch|64}} [[ARM]] [[LTE]] SoC introduced by [[MediaTek]] in mid [[2019]]. Fabricated on TSMC's [[12 nm process]], the chip incorporates eight cores - two {{armh|Cortex-A75|l=arch}} [[big cores]] and six {{armh|Cortex-A55|l=arch}} [[little cores]] operating at up to 2 Ghz. The P65 incorporates a {{armh|Mali-G52}} GPU operating at up to 820 MHz and an LTE modem supporting Cat-13 150 Mbps upload and Cat-7 300 Mbps download. This chip supports up to 8 GiB of single-channel LPDDR4X-3600 memory.</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=hisilicon/kirin/810&diff=92077
hisilicon/kirin/810
2019-06-21T13:07:29Z
<p>87.214.221.129: Created Kirin 810 page</p>
<hr />
<div>{{hisil title|Kirin 810}}<br />
{{chip<br />
|name=Kirin 810<br />
|no image=No<br />
|designer=HiSilicon<br />
|designer 2=ARM Holdings<br />
|manufacturer=TSMC<br />
|model number=810<br />
|market=Mobile<br />
|first announced=June 21, 2019<br />
|first launched=June 21, 2019<br />
|family=Kirin<br />
|series=800<br />
|frequency=2,270 MHz<br />
|frequency 2=1,800 MHz<br />
|isa=ARMv8<br />
|isa family=ARM<br />
|microarch=Cortex-A76<br />
|microarch 2=Cortex-A55<br />
|core name=Cortex-A76<br />
|core name 2=Cortex-A55<br />
|process=7 nm<br />
|technology=CMOS<br />
|word size=64 bit<br />
|core count=8<br />
|thread count=8<br />
|max cpus=1<br />
|max memory=<br />
}}<br />
'''Kirin 810''' is a {{arch|64}} [[octa-core]] mid-range performance mobile [[ARM]] SoC introduced by [[HiSilicon]] in mid-[[2019]]. This chip, which is fabricated on [[TSMC]]'s [[7 nm process]], features two {{armh|Cortex-A76|l=arch}} [[big cores]] operating at up to 2.27 GHz along with six {{armh|Cortex-A55}} [[little cores]] operating at up to 1.8 GHz. The 810 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali-G52}} MP6 GPU.<br />
<br />
== Utilizing devices ==<br />
* [[used by::Huawei Nova 5]]</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=hisilicon/kirin&diff=92076
hisilicon/kirin
2019-06-21T12:58:53Z
<p>87.214.221.129: /* Members */ Added 800 series and Kirin 810</p>
<hr />
<div>{{hisil title|Kirin}}<br />
{{ic family<br />
| title = Kirin<br />
| image = hisilicon kirin logo.svg<br />
| caption = Kirin Logo<br />
| developer = HiSilicon<br />
| developer 2 = ARM Holdings<br />
| manufacturer = TSMC<br />
| type = System on chips<br />
| first announced = 2013<br />
| first launched = 2014<br />
| arch = Performance mobile ARM SoCs<br />
| isa = ARM<br />
| microarch = Cortex-A7<br />
| microarch 2 = Cortex-A9<br />
| microarch 3 = Cortex-A53<br />
| microarch 4 = Cortex-A72<br />
| microarch 5 = Cortex-A73<br />
| word = 32 bit<br />
| word 2 = 64 bit<br />
| proc = 28 nm<br />
| proc 2 = 16 nm<br />
| proc 3 = 10 nm<br />
| proc 4 = 7 nm<br />
| tech = CMOS<br />
| clock min = 1,200 MHz<br />
| clock max = 2,300 MHz<br />
| package = <br />
| package 2 = <br />
| package 3 = <br />
<br />
| succession = Yes<br />
| predecessor = K3<br />
| predecessor link = hisilicon/k3<br />
| successor = <br />
| successor link = <br />
}}<br />
'''Kirin''' is a family of {{arch|32}} and {{arch|64}} mobile [[ARM]] performance SoCs introduced by [[HiSilicon]] in [[2014]] as a successor to the {{\\|K3}} series.<br />
<br />
== Overview ==<br />
HiSilicon has always been the [[integrated circuit]] arm of [[Huawei]], developing various ICs and embedded [[microprocessors]] for their consumer electronics. It wasn't until [[2008]] with the introduction of the {{\\|K3}} family that [[HiSilicon]] started focusing on developing in-house high-performance microprocessors for the mobile market. In late [[2013]] HiSilicon introduced the Kirin family which featured their flagship high-performance mobile microprocessors found in their high-end phones and tablets.<br />
<br />
Over the last couple of years, the Kirin family grew to include various mid-range performance models in addition to their high-end performance flagship processors. Latest models often utilize [[ARM Holdings|ARM]]'s latest cores fabricated on [[TSMC]]'s latest [[technology node]].<br />
<br />
== Members ==<br />
<br />
=== 600 Series ===<br />
[https://www.google.com/search?q=Kirin+620 Kirin 620]<br /><br />
<br />
[https://www.google.com/search?q=Kirin+650 Kirin 650]<br />
<br />
=== 700 Series ===<br />
[[Kirin 710]]<br />
<br />
=== 800 Series ===<br />
[[Kirin 810]]<br />
<br />
=== 900 Series ===<br />
[https://www.google.com/search?q=Kirin+910 Kirin 910]<br /><br />
[https://www.google.com/search?q=Kirin+920 Kirin 920]<br /><br />
[https://www.google.com/search?q=Kirin+930 Kirin 930]<br /><br />
[https://www.google.com/search?q=Kirin+950 Kirin 950]<br /><br />
[https://www.google.com/search?q=Kirin+960 Kirin 960]<br /><br />
[[Kirin 970]]<br /><br />
[[Kirin 980]]</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=WikiChip:wanted_chips&diff=92070
WikiChip:wanted chips
2019-06-20T22:33:46Z
<p>87.214.221.129: /* ARM SoC Chips */ Add Amlogic S905X3</p>
<hr />
<div>{{wikichip wanted}}'''The following wanted/requested chips should be documented.''' Stopping by to list a missing chip? Fantastic! just add its name to the list! If it's a really obscure chip, a link to a source wouldn't hurt!<br />
<br />
= Missing/Requested/Wanted chips list =<br />
* Tilera / Mellanox<br />
* MIT Raw http://groups.csail.mit.edu/cag/raw/<br />
* [[Transmeta]] / [[Crusoe]] / [[Efficeon]]<br />
* [[Nvidia]] Project [[nvidia/denver|denver]]<br />
* pretty much everything listed here http://ps-2.kev009.com/powerpc-faq/<br />
* [[Quantum Effect Device]]/[[Quantum Effect Designs]] / [[PowerPC 603q]] / etc..<br />
* Stretch S5000<br />
* [[Kalray]] / [[MPPA-256]] / [[MPPA2-256]]<br />
* [[Sunway TaihuLight]]<br />
** [[ShenWei]] / [[SW26010]] / [[SW1600]] / [[SW-1]]/[[SW-2]]/[[SW-3]]<br />
* Godson-1 September 28, 2002 Godson-2/Godson-3 - Institute of Computing Technology, Chinese Academy of Sciences<br />
* Intersil ISD-8, was announced in 1994 (can see it [http://chiclassiccomp.org/docs/content/publications/ACS_Newsletter/ACS_Newsletter_3_7.pdf here], and [https://books.google.com/books?id=XeazBgAAQBAJ&lpg=PA72&ots=eR_z2Or3Cf&dq=fairchild%20PPS-25&pg=PA72#v=onepage&q&f=false here]) unknown if ever released or was codename possibly or the Intersil 6100<br />
* Mostek MK5065<br />
* Infineon Carmel DSP<br />
* TCL41, 43, 45 <br />
* [[Intel Pentium A1020]]<br />
* [http://apt.cs.manchester.ac.uk/projects/SpiNNaker/hardware/ SpiNNaker]<br />
* Crypto CoPros<br />
** IBM 4758<br />
** IBM 4578<br />
** IBM 4765<br />
** IBM 4764<br />
** IBM 4764-001 [https://www-03.ibm.com/security/cryptocards/pciecc/pdf/PCIe_Spec_Sheet.pdf src]<br />
* [[Intel 8031]]<br />
* [[Intel 8035]]<br />
* [[Intel 8039]]<br />
* [[Intel 8048]]<br />
* [[Intel 8051]]<br />
* [[Intel 8086]]<br />
* [[Intel 8087]]<br />
* [[Intel 8088]]<br />
* [[Intel 8748]]<br />
* [[Intel 8751]]<br />
* [[Intel 80186]]<br />
* [[Intel 80188]]<br />
* [[Intel 80286]]<br />
* [[Intel 80376]]<br />
* [[Intel 80486]]<br />
* [[Intel 80486 overdrive]]<br />
* [[Intel 80860]]<br />
* [[Intel n80960]]<br />
* [[Intel Pentium II]]<br />
* [[Intel Pentium MMX]]<br />
* [[Intel Pentium III]]<br />
* [[Intel Pentium G3258]]<br />
(list not complete)<br />
<br />
4-bit ones<br />
* [[TLCS-47]]<br />
<br />
Some 8-bit ones<br />
* [[Intel 8080]]<br />
* [[Intel 8085]]<br />
* [[Burroughs Mini-D]]<br />
* [[Mostek 5065]]<br />
* [[MOS Technology 6502]]<br />
* [[Motorola 6800]]<br />
* [[Motorola 6809]]<br />
* [[Motorola 6801]]<br />
* [[Motorola 6803]]<br />
* [[National SC/MP]]<br />
* [[Signetics 2650]]<br />
* [[Rockwell PPS-8]]<br />
* [[RCA COSMAC 1802]]<br />
* [[RCA COSMAC 1802]]<br />
* [[Zilog Z8]]<br />
* [[Zilog Z80]]<br />
* [[Zilog eZ80]]<br />
* [[Zilog Z180]]<br />
* [[Signetics 8X300]]<br />
* [[Freescale HC08]]<br />
* [[Freescale HC11]]<br />
* [[Hudson Soft HuC6280]]<br />
* [[microchip/PIC10]]<br />
* [[microchip/PIC12]]<br />
* [[microchip/PIC16]]<br />
* [[Ricoh 2A03]]<br />
* [[Ricoh 2A07]]<br />
* [[TLCS-870]]<br />
* [[National COP8]]<br />
* [[AMI 7200]]<br />
* [[Intel Core i7-7700HQ]] (Kaby Lake-H, quad-core 2.8 GHz, 45W)<br />
* [[atmel/atmega]], in particular the Atmel ATmega328 used in most Arduino boards<br />
* [[cypress/PSoC 1]]<br />
* [[cypress/PSoC 4]]<br />
* [[cypress/PSoC 5]]<br />
* [[parallax/Basic Stamp]]<br />
[[File:Basic stamp 2p24.jpg|thumb|right|200px|[[Parallax]]'s Basic Stamp 2 board ({{parallax|BS2P24}}). This board has a [[CPU]] and a [[BASIC]] [[interpreter]] on-board. (from [[program]]).]]<br />
* [[parallax/Propeller]]<br />
* [[Nios II]] softcore CPU for FPGA<br />
* [[MicroBlaze]] softcore CPU for FPGA<br />
* [[DLX]] by John L. Hennessy and David A. Patterson<br />
* [[Elbrus]]<br />
* GreenArrays (asynchronous) F18A/F18B GA4/GA32/GA40/GA144<br />
* [[Sun]] {{sun|Rock}}<br />
* [[NovaThor]]<br />
* [[MediaTek MT6735]]<br />
* [[Microsoft Xenon]]<br />
* [[Nordic Semiconductor nRF52832]]<br />
* [[Nordic Semiconductor nRF52840]]<br />
<br />
* [[Intel Xeon X5670]]<br />
* [[Intel Xeon X5690]]<br />
<br />
== ARM SoC Chips ==<br />
<br />
* [[Spreadtrum SC9863]] (8x [[Cortex-A55]] at 1.6 GHz)<br />
* [[Amlogic S905X3]] (4x [[Cortex-A55]], [[Mali-G31]]MP2)<br />
<br />
List copied from http://linux-sunxi.org/Allwinner_SoC_Family<br />
<br />
=== A series ===<br />
<br />
* [[Allwinner A10]] (sun4i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A13]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A10s]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A20]] (sun7i) 2 x Cortex-A7 CPU-cores<br />
* [[Allwinner A23]] (sun8i) 2 x Cortex-A7 CPU-cores<br />
* [[Allwinner A31]] (sun6i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A31s]] (sun6i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A33]] (sun8i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A80]] (sun9i) 4 x Cortex-A7 CPU-cores + 4 x Cortex-A15 CPU-cores <br />
* [[Allwinner A83T]] (sun8i) 8 x Cortex-A7 CPU-cores<br />
* [[Allwinner A64]] (sun50i) 4 x Cortex-A53 CPU-core<br />
<br />
=== H series ===<br />
<br />
* [[Allwinner H2+]] (sun8i) 4 x Cortex-A7 CPU-core <br />
* [[Allwinner H3]] (sun8i) 4 x Cortex-A7 CPU-core <br />
* [[Allwinner H8]] (sun8i) 8 x Cortex-A7 CPU-core<br />
* [[Allwinner H5]] (sun50i) 4 x Cortex-A53 CPU-core<br />
* [[Allwinner H6]] (sun50i) 4 x Cortex-A53 CPU-core<br />
* [[Allwinner H64]] (sun50i) 4 x Cortex-A53 CPU-core<br />
<br />
=== R series ===<br />
<br />
* [[Allwinner R8]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner R16]] (sun8i) 4 x Cortex-A7 CPU-core<br />
* [[Allwinner R40]] (sun8i) 4 x Cortex-A7 CPU-core<br />
* [[Allwinner R58]] (sun8i) 8 x Cortex-A7 CPU-core<br />
<br />
=== V series ===<br />
<br />
* [[Allwinner V3]] (sun8i) 1 x Cortex-A7 CPU-core<br />
* [[Allwinner V3s]] (sun8i) 1 x Cortex-A7 CPU-core<br />
* [[Allwinner V40]] (sun8i) 4 x Cortex-A7 CPU-core<br />
<br />
=== F series ===<br />
<br />
* [[Boxchip C100]] (sun3i)<br />
* [[Boxchip E200]] (sun3i)<br />
* [[Boxchip F20]] (sun3i)<br />
* [[Boxchip F10]] aka SoChip SC9800 aka Teclast T8100 (sunii)<br />
* [[Boxchip F13]] (sunii)<br />
* [[Boxchip F15]] aka SoChip SC8600 aka Teclast T7200 (sunii)<br />
* [[Boxchip F18]] (sunii)<br />
* [[Allwinner F1C100s]] (suniv)<br />
* [[Allwinner F1C600]] (suniv)<br />
* [[Allwinner F1C100A]] (suniv)<br />
* [[Allwinner F1C700]] (sun5i)</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=WikiChip:wanted_chips&diff=92069
WikiChip:wanted chips
2019-06-20T22:31:40Z
<p>87.214.221.129: /* Missing/Requested/Wanted chips list */ Added Spreadtrum SC9863</p>
<hr />
<div>{{wikichip wanted}}'''The following wanted/requested chips should be documented.''' Stopping by to list a missing chip? Fantastic! just add its name to the list! If it's a really obscure chip, a link to a source wouldn't hurt!<br />
<br />
= Missing/Requested/Wanted chips list =<br />
* Tilera / Mellanox<br />
* MIT Raw http://groups.csail.mit.edu/cag/raw/<br />
* [[Transmeta]] / [[Crusoe]] / [[Efficeon]]<br />
* [[Nvidia]] Project [[nvidia/denver|denver]]<br />
* pretty much everything listed here http://ps-2.kev009.com/powerpc-faq/<br />
* [[Quantum Effect Device]]/[[Quantum Effect Designs]] / [[PowerPC 603q]] / etc..<br />
* Stretch S5000<br />
* [[Kalray]] / [[MPPA-256]] / [[MPPA2-256]]<br />
* [[Sunway TaihuLight]]<br />
** [[ShenWei]] / [[SW26010]] / [[SW1600]] / [[SW-1]]/[[SW-2]]/[[SW-3]]<br />
* Godson-1 September 28, 2002 Godson-2/Godson-3 - Institute of Computing Technology, Chinese Academy of Sciences<br />
* Intersil ISD-8, was announced in 1994 (can see it [http://chiclassiccomp.org/docs/content/publications/ACS_Newsletter/ACS_Newsletter_3_7.pdf here], and [https://books.google.com/books?id=XeazBgAAQBAJ&lpg=PA72&ots=eR_z2Or3Cf&dq=fairchild%20PPS-25&pg=PA72#v=onepage&q&f=false here]) unknown if ever released or was codename possibly or the Intersil 6100<br />
* Mostek MK5065<br />
* Infineon Carmel DSP<br />
* TCL41, 43, 45 <br />
* [[Intel Pentium A1020]]<br />
* [http://apt.cs.manchester.ac.uk/projects/SpiNNaker/hardware/ SpiNNaker]<br />
* Crypto CoPros<br />
** IBM 4758<br />
** IBM 4578<br />
** IBM 4765<br />
** IBM 4764<br />
** IBM 4764-001 [https://www-03.ibm.com/security/cryptocards/pciecc/pdf/PCIe_Spec_Sheet.pdf src]<br />
* [[Intel 8031]]<br />
* [[Intel 8035]]<br />
* [[Intel 8039]]<br />
* [[Intel 8048]]<br />
* [[Intel 8051]]<br />
* [[Intel 8086]]<br />
* [[Intel 8087]]<br />
* [[Intel 8088]]<br />
* [[Intel 8748]]<br />
* [[Intel 8751]]<br />
* [[Intel 80186]]<br />
* [[Intel 80188]]<br />
* [[Intel 80286]]<br />
* [[Intel 80376]]<br />
* [[Intel 80486]]<br />
* [[Intel 80486 overdrive]]<br />
* [[Intel 80860]]<br />
* [[Intel n80960]]<br />
* [[Intel Pentium II]]<br />
* [[Intel Pentium MMX]]<br />
* [[Intel Pentium III]]<br />
* [[Intel Pentium G3258]]<br />
(list not complete)<br />
<br />
4-bit ones<br />
* [[TLCS-47]]<br />
<br />
Some 8-bit ones<br />
* [[Intel 8080]]<br />
* [[Intel 8085]]<br />
* [[Burroughs Mini-D]]<br />
* [[Mostek 5065]]<br />
* [[MOS Technology 6502]]<br />
* [[Motorola 6800]]<br />
* [[Motorola 6809]]<br />
* [[Motorola 6801]]<br />
* [[Motorola 6803]]<br />
* [[National SC/MP]]<br />
* [[Signetics 2650]]<br />
* [[Rockwell PPS-8]]<br />
* [[RCA COSMAC 1802]]<br />
* [[RCA COSMAC 1802]]<br />
* [[Zilog Z8]]<br />
* [[Zilog Z80]]<br />
* [[Zilog eZ80]]<br />
* [[Zilog Z180]]<br />
* [[Signetics 8X300]]<br />
* [[Freescale HC08]]<br />
* [[Freescale HC11]]<br />
* [[Hudson Soft HuC6280]]<br />
* [[microchip/PIC10]]<br />
* [[microchip/PIC12]]<br />
* [[microchip/PIC16]]<br />
* [[Ricoh 2A03]]<br />
* [[Ricoh 2A07]]<br />
* [[TLCS-870]]<br />
* [[National COP8]]<br />
* [[AMI 7200]]<br />
* [[Intel Core i7-7700HQ]] (Kaby Lake-H, quad-core 2.8 GHz, 45W)<br />
* [[atmel/atmega]], in particular the Atmel ATmega328 used in most Arduino boards<br />
* [[cypress/PSoC 1]]<br />
* [[cypress/PSoC 4]]<br />
* [[cypress/PSoC 5]]<br />
* [[parallax/Basic Stamp]]<br />
[[File:Basic stamp 2p24.jpg|thumb|right|200px|[[Parallax]]'s Basic Stamp 2 board ({{parallax|BS2P24}}). This board has a [[CPU]] and a [[BASIC]] [[interpreter]] on-board. (from [[program]]).]]<br />
* [[parallax/Propeller]]<br />
* [[Nios II]] softcore CPU for FPGA<br />
* [[MicroBlaze]] softcore CPU for FPGA<br />
* [[DLX]] by John L. Hennessy and David A. Patterson<br />
* [[Elbrus]]<br />
* GreenArrays (asynchronous) F18A/F18B GA4/GA32/GA40/GA144<br />
* [[Sun]] {{sun|Rock}}<br />
* [[NovaThor]]<br />
* [[MediaTek MT6735]]<br />
* [[Microsoft Xenon]]<br />
* [[Nordic Semiconductor nRF52832]]<br />
* [[Nordic Semiconductor nRF52840]]<br />
<br />
* [[Intel Xeon X5670]]<br />
* [[Intel Xeon X5690]]<br />
<br />
== ARM SoC Chips ==<br />
<br />
* [[Spreadtrum SC9863]] (8x [[Cortex-A55]] at 1.6 GHz)<br />
<br />
List copied from http://linux-sunxi.org/Allwinner_SoC_Family<br />
<br />
=== A series ===<br />
<br />
* [[Allwinner A10]] (sun4i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A13]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A10s]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner A20]] (sun7i) 2 x Cortex-A7 CPU-cores<br />
* [[Allwinner A23]] (sun8i) 2 x Cortex-A7 CPU-cores<br />
* [[Allwinner A31]] (sun6i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A31s]] (sun6i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A33]] (sun8i) 4 x Cortex-A7 CPU-cores<br />
* [[Allwinner A80]] (sun9i) 4 x Cortex-A7 CPU-cores + 4 x Cortex-A15 CPU-cores <br />
* [[Allwinner A83T]] (sun8i) 8 x Cortex-A7 CPU-cores<br />
* [[Allwinner A64]] (sun50i) 4 x Cortex-A53 CPU-core<br />
<br />
=== H series ===<br />
<br />
* [[Allwinner H2+]] (sun8i) 4 x Cortex-A7 CPU-core <br />
* [[Allwinner H3]] (sun8i) 4 x Cortex-A7 CPU-core <br />
* [[Allwinner H8]] (sun8i) 8 x Cortex-A7 CPU-core<br />
* [[Allwinner H5]] (sun50i) 4 x Cortex-A53 CPU-core<br />
* [[Allwinner H6]] (sun50i) 4 x Cortex-A53 CPU-core<br />
* [[Allwinner H64]] (sun50i) 4 x Cortex-A53 CPU-core<br />
<br />
=== R series ===<br />
<br />
* [[Allwinner R8]] (sun5i) 1 x Cortex-A8 CPU-core<br />
* [[Allwinner R16]] (sun8i) 4 x Cortex-A7 CPU-core<br />
* [[Allwinner R40]] (sun8i) 4 x Cortex-A7 CPU-core<br />
* [[Allwinner R58]] (sun8i) 8 x Cortex-A7 CPU-core<br />
<br />
=== V series ===<br />
<br />
* [[Allwinner V3]] (sun8i) 1 x Cortex-A7 CPU-core<br />
* [[Allwinner V3s]] (sun8i) 1 x Cortex-A7 CPU-core<br />
* [[Allwinner V40]] (sun8i) 4 x Cortex-A7 CPU-core<br />
<br />
=== F series ===<br />
<br />
* [[Boxchip C100]] (sun3i)<br />
* [[Boxchip E200]] (sun3i)<br />
* [[Boxchip F20]] (sun3i)<br />
* [[Boxchip F10]] aka SoChip SC9800 aka Teclast T8100 (sunii)<br />
* [[Boxchip F13]] (sunii)<br />
* [[Boxchip F15]] aka SoChip SC8600 aka Teclast T7200 (sunii)<br />
* [[Boxchip F18]] (sunii)<br />
* [[Allwinner F1C100s]] (suniv)<br />
* [[Allwinner F1C600]] (suniv)<br />
* [[Allwinner F1C100A]] (suniv)<br />
* [[Allwinner F1C700]] (sun5i)</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=intel/microarchitectures/ice_lake_(client)&diff=91284
intel/microarchitectures/ice lake (client)
2019-05-28T11:01:19Z
<p>87.214.221.129: /* SoC */ Added die size</p>
<hr />
<div>{{intel title|Ice Lake (client)|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Ice Lake (client)<br />
|designer=Intel<br />
|manufacturer=Intel<br />
|introduction=2019<br />
|process=10 nm<br />
|isa=x86-64<br />
|l1i=32 KiB<br />
|l1i per=core<br />
|l1i desc=8-way set associative<br />
|l1d=48 KiB<br />
|l1d per=core<br />
|l1d desc=12-way set associative<br />
|l1 per=core<br />
|l2=512 KiB<br />
|l2 per=512 KiB<br />
|l2 desc=12-way set associative<br />
|l3=2 MiB<br />
|l3 per=core<br />
|l3 desc=16-way set associative<br />
|core name=Ice Lake Y<br />
|core name 2=Ice Lake U<br />
|predecessor=Cannon Lake<br />
|predecessor link=intel/microarchitectures/cannon lake<br />
|successor=Tiger Lake<br />
|successor link=intel/microarchitectures/tiger lake<br />
|contemporary=Ice Lake (server)<br />
|contemporary link=intel/microarchitectures/ice_lake_(server)<br />
}}<br />
'''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices.<br />
<br />
== Codenames ==<br />
{| class="wikitable"<br />
|-<br />
! Core !! Abbrev !! Description !! Graphics !! Target<br />
|-<br />
| {{intel|Ice Lake Y|l=core}} || ICL-Y || Extremely low power || || 2-in-1s detachable, tablets, and computer sticks<br />
|-<br />
| {{intel|Ice Lake U|l=core}} || ICL-U || Ultra-low Power || || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room<br />
|-<br />
| {{intel|Ice Lake H|l=core}} || ICL-H || High-performance Graphics || || Ultimate mobile performance, mobile workstations<br />
|-<br />
| <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s><br />
|}<br />
<br />
== Process Technology==<br />
{{see also|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}<br />
Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.<br />
<br />
[[File:intels 10+ and 10++.png|750px]]<br />
<br />
{{clear}}<br />
<br />
== Compiler support ==<br />
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.<br />
{| class="wikitable"<br />
|-<br />
! Compiler !! Arch-Specific || Arch-Favorable<br />
|-<br />
| [[ICC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code><br />
|-<br />
| [[GCC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code><br />
|-<br />
| [[LLVM]] || <code>-march=icelake</code> || <code>-mtune=icelake</code><br />
|-<br />
| [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code><br />
|}<br />
<br />
=== CPUID ===<br />
{| class="wikitable tc1 tc2 tc3 tc4"<br />
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model<br />
|-<br />
| rowspan="2" | {{intel|Ice Lake U|U|l=core}}, {{intel|Ice Lake Y|Y|l=core}} || 0 || 0x6 || 0x7 || 0xE<br />
|-<br />
| colspan="4" | Family 6 Model 126<br />
|-<br />
| rowspan="2" | ? || 0 || 0x6 || ? || ?<br />
|-<br />
| colspan="4" | Family 6 Model ?<br />
|}<br />
<br />
== Architecture ==<br />
Ice Lake comprises of {{\\|Sunny Cove}} cores on the {{intel|ring interconnect architecture}} along with {{\\|Gen11}} GPU, and an improved {{intel|System Agent}} with a new display engine and I/O.<br />
<br />
=== Key changes from {{\\|Cannon Lake}}/{{\\|Skylake}}===<br />
* Enhanced "10nm+" (from "10nm", 2nd gen)<br />
* Core<br />
** {{\\|Sunny Cove|Sunny Cove core}} (from {{\\|Palm Cove}})<br />
*** ''See {{\\|Sunny Cove}} for microarchitectural details and changes''<br />
* Memory<br />
** 4 32-bit [[LPDDR4X]] channels (from 2 64-bit [[DDR4]] channels)<br />
** 1.4x higher data rates (3733 MT/s, up from 2666 MT/s)<br />
*** 1.5x higher memory bandwidth (60 GB/s, up from 40 GB/s)<br />
* Graphics<br />
** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'')<br />
** {{intel|Gen11|l=arch}} GPUs<br />
*** UHD Graphics 6xx (GT1) '''→''' UHD Graphics 9xx (GT2) (24 Execution Units, 2x EUs from {{\\|Gen9}})<br />
*** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}})<br />
**** 1,024 GFLOPS @ 1 GHz (GT2)<br />
* Display<br />
** Gen 11.5 (from Gen9/Gen9.5)<br />
** DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2)<br />
** HDMI 2.0 (from HDMI 1.4)<br />
* IPU<br />
** 4th Gen IPU (from 3rd Gen in {{\\|Skylake (client)|Skylake}})<br />
** More cameras support<br />
** New concurrent image pipeline<br />
** on-die MIPI interface<br />
* I/O<br />
** Thunderbolt 3 over Type-C<br />
<br />
{{expand list}}<br />
<br />
====New instructions ====<br />
Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.<br />
<br />
=== Block Diagram ===<br />
<br />
==== Entire SoC Overview ====<br />
[[File:ice lake soc block diagram.svg|900px]]<br />
<br />
==== Individual Core ====<br />
See {{intel|Sunny Cove#Block Diagram|Sunny Cove § Block Diagram|l=arch}}.<br />
<br />
==== Gen11 Graphics ====<br />
See {{intel|Gen11#Block Diagram|Gen11 Graphics § Block Diagram|l=arch}}.<br />
<br />
== Overview ==<br />
{{empty section}}<br />
<br />
== Core ==<br />
{{empty section}}<br />
<br />
== IPU ==<br />
Ice Lake incorporates 4th generation [[image processing unit]] (IPU). The IPU was first introduced with {{\\|Skylake (client)|Skylake}} mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements.<br />
<br />
== Clock domains ==<br />
Ice Lake is divided into a number of [[clock domains]], each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).<br />
<br />
* '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual [[FSB]] speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.<br />
* '''Core Clock''' - The frequency at which the core and the [[L1]]/[[L2]] caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).<br />
* '''Ring Clock''' - The frequency at which the ring interconnect and [[L3$|LLC]] operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.<br />
* '''IGP Clock''' - The frequency at which the [[integrated graphics]] ({{\\|Gen11}} GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.<br />
* '''IPU''' - The frequency at which the [[image processing unit]] operates at<br />
* '''MemClk''' - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transferred at a rate of 8B/cycle operating at MemClk frequency.<br />
<br />
[[File:ice lake soc clock domain block diagram.svg|850px]]<br />
<br />
== Die ==<br />
=== System Agent ===<br />
* System Agent<br />
** 4th Gen IPU<br />
** Gen11 Display<br />
** Thunderbolt 3 over Type-C<br />
** PCIe<br />
<br />
<br />
:[[File:ice lake die sa.png|700px]]<br />
<br />
<br />
:[[File:ice lake die sa (annotated).png|700px]]<br />
<br />
=== Core ===<br />
:[[File:ice lake die core.png|400px]]<br />
<br />
<br />
:[[File:ice lake die core (annotated).png|400px]]<br />
<br />
=== Core group ===<br />
:[[File:ice lake die core group.png|700px]]<br />
<br />
<br />
:[[File:ice lake die core group (annotated).png|700px]]<br />
<br />
=== Integrated graphics ===<br />
:[[File:ice lake die gpu.png|700px]]<br />
<br />
<br />
:[[File:ice lake die gpu (annotated).png|700px]]<br />
<br />
=== SoC ===<br />
* [[10 nm process]]<br />
* 4 {{\\|Sunny Cove}} [[big cores]]<br />
* 64-EU {{\\|Gen11}} GPU<br />
* 4th Gen IPU<br />
* Aprox. 130mm<sup>2</sup> die size<br />
<br />
:[[File:ice lake die (quad core).png|700px]]<br />
<br />
<br />
:[[File:ice lake die (quad core) (annotated).png|700px]]<br />
<br />
== All Ice Lake Chips ==<br />
{{future information}}<br />
<br />
<!-- NOTE: <br />
This table is generated automatically from the data in the actual articles.<br />
If a microprocessor is missing from the list, an appropriate article for it needs to be<br />
created and tagged accordingly.<br />
<br />
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips<br />
--><br />
{{comp table start}}<br />
<table class="comptable sortable tc7 tc8 tc20 tc21"><br />
{{comp table header|main|20:List of Ice Lake-based Processors}}<br />
{{comp table header|main|10:Main processor|4:{{intel|Turbo Boost}}|Memory|3:GPU|2:Features}}<br />
{{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|1 Core|2 Cores|4 Cores|6 Cores|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}}<br />
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]]<br />
|?full page name<br />
|?model number<br />
|?first launched<br />
|?release price<br />
|?microprocessor family<br />
|?platform<br />
|?core name<br />
|?core count<br />
|?thread count<br />
|?l3$ size<br />
|?tdp<br />
|?base frequency#GHz<br />
|?turbo frequency (1 core)#GHz<br />
|?turbo frequency (2 cores)#GHz<br />
|?turbo frequency (4 cores)#GHz<br />
|?turbo frequency (6 cores)#GHz<br />
|?max memory#GiB<br />
|?integrated gpu<br />
|?integrated gpu base frequency<br />
|?integrated gpu max frequency<br />
|?has intel turbo boost technology 2_0<br />
|?has simultaneous multithreading<br />
|format=template<br />
|template=proc table 3<br />
|userparam=21<br />
|mainlabel=-<br />
}}<br />
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]]}}<br />
</table><br />
{{comp table end}}<br />
<br />
== Bibliography ==<br />
* Intel 2018 Architecture Day.<br />
* Intel. ''personal communication''. 2019.</div>
87.214.221.129
https://en.wikichip.org/w/index.php?title=xiaomi/surge/s1&diff=68840
xiaomi/surge/s1
2017-12-06T12:32:15Z
<p>87.214.221.129: Added MP4 GPU</p>
<hr />
<div>{{xiaomi title|Surge S1}}<br />
{{mpu<br />
| future = Yes<br />
| name = Xiaomi Surge S1<br />
| no image = Yes<br />
| image = <br />
| image size = <br />
| caption = <br />
| designer = Xiaomi<br />
| designer 2 = ARM Holdings<br />
| manufacturer = TSMC<br />
| model number = S1<br />
| part number = <br />
| part number 2 = <br />
| part number 3 = <br />
| part number 4 = <br />
| market = Mobile<br />
| first announced = February 28, 2017<br />
| first launched = <br />
| last order = <br />
| last shipment = <br />
| release price = <br />
<br />
| family = Surge<br />
| series = <br />
| locked = <br />
| frequency = 1,400 MHz<br />
| frequency 2 = 2,200 MHz<br />
| bus type = AXI<br />
| bus speed = <br />
| bus rate = <br />
| clock multiplier = <br />
<br />
| isa family = ARM<br />
| isa = ARMv8<br />
| microarch = Cortex-A53<br />
| platform = <br />
| chipset = <br />
| core name = Cortex-A53<br />
| core family = <br />
| core model = <br />
| core stepping = <br />
| process = 28 nm<br />
| transistors = <br />
| technology = CMOS<br />
| die area = <!-- mm² --><br />
| die width = <br />
| die length = <br />
| word size = <br />
| core count = 8<br />
| thread count = 8<br />
| max cpus = <br />
| max memory = <br />
| max memory addr = <br />
<br />
| electrical = <br />
| power = <br />
| v core = <br />
| v core tolerance = <br />
| v core min = <br />
| v core max = <br />
| v io = <br />
| v io tolerance = <br />
| v io 2 = <!-- OR ... --><br />
| v io 3 = <br />
| sdp = <br />
| tdp = <br />
| tdp typical = <br />
| ctdp down = <br />
| ctdp down frequency = <br />
| ctdp up = <br />
| ctdp up frequency = <br />
| temp min = <br />
| temp max = <br />
| tjunc min = <!-- °C --><br />
| tjunc max = <br />
| tcase min = <br />
| tcase max = <br />
| tstorage min = <br />
| tstorage max = <br />
| tambient min = <br />
| tambient max = <br />
<br />
| packaging = <br />
| package 0 = <br />
| package 0 type = <br />
| package 0 pins = <br />
| package 0 pitch = <br />
| package 0 width = <br />
| package 0 length = <br />
| package 0 height = <br />
| socket 0 = <br />
| socket 0 type = <br />
}}<br />
[[File:surge s1 dev roadmap.jpg|thumb|right]]<br />
[[File:surge s1 block.jpg|400px|right]]<br />
'''Surge S1''' is a {{arch|64}} [[octa-core]] performance [[ARM]] system-on-chip designed by [[Xiaomi]] and introduced in early [[2017]]. This chip incorporates 8 {{armh|Cortex-A53}} cores in a {{armh|big.LITTLE}} configuration with four cores operating at up to 2.2 GHz with the other four set of cores operating at 1.4 GHz. This processor is fabricated on TSMC's [[28 nm process|28 nm HPC+ process]] and incorporates a {{armh|Mali-T860}} MP4 [[IGP]]. The S1 is Xiaomi's first generation in-house developed system-on-chip.<br />
<br />
<br />
{{unknown features}}<br />
<br />
<br />
== Memory controller ==<br />
{{memory controller<br />
|type=LPDDR3-1866<br />
|ecc=No<br />
|controllers=1<br />
|channels=2<br />
|width=32 bit<br />
|max bandwidth=13.91 GiB/s<br />
|bandwidth schan=6.95<br />
|bandwidth dchan=13.91 GiB/s<br />
}}<br />
<br />
== Graphics ==<br />
{{integrated graphics<br />
| gpu = Mali-T860 MP4<br />
| device id = <br />
| designer = ARM Holdings<br />
| execution units = 4<br />
| max displays = <br />
| max memory = <br />
| frequency = 800 MHz<br />
<br />
| output dsi = Yes<br />
<br />
| max res dsi = 2560×1600<br />
<br />
| direct3d ver = 11.2<br />
| opencl ver = 1.2<br />
| opengl ver = 3.2<br />
| opengl es ver = 3.2<br />
| vulkan ver = 1.0<br />
| openvg ver = 1.1<br />
}}<br />
<br />
== Image ==<br />
* AFBC + ASTC<br />
* 14-bit dual ISP<br />
<br />
== Video ==<br />
* Video capturing 4K@30fps, 1080p@120fps, 720p@240/fps<br />
* H.265/HEVC (Main profile)<br />
* H.264 (Baseline/Main/High profile)<br />
* MPEG4 (Simple profile/ASP),<br />
* VC-1(Simple/Main/Advanced profile)<br />
<br />
== Utilizing devices ==<br />
* [[used by::Xiaomi Mi 5C]]<br />
<br />
{{expand list}}</div>
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