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https://en.wikichip.org/w/index.php?title=mips/mips32_instruction_set&diff=94363
mips/mips32 instruction set
2019-11-09T12:24:06Z
<p>77.243.191.41: Typo</p>
<hr />
<div>{{mips title|MIPS32 Instruction Set}}<br />
{{ISA|<br />
|name = MIPS32<br />
|designer = [[MIPS Technologies, Inc.]]<br />
|bits = 32-bits<br />
|introduced = 1999<br />
|version = Revision 5.3<br />
|design = RISC<br />
|type = Register-Register<br />
|encoding = Fixed-length<br />
|branching = Condition Register<br />
|endianness = Bi-endian<br />
|extensions = {{mips|SPECIAL2}}, {{mips|COP2}}, {{mips|LWC2}}, {{mips|SWC2}}, {{mips|LDC2}}, {{mips|SDC2}}<br />
|application = {{mips|MIPS16e}}, {{mips|MCU}}, {{mips|SmartMIPS}}<br />
|multimedia = {{mips|MIPS-3D}}<br />
|gpr = 32<br />
|fpr = 32<br />
|spr = {{mips|PRId register|PRId}}<br />
}}<br />
<br />
The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the {{mips|MIPS64 Instruction Set}} which includes 64-bit instructions. The MIP32 standard included {{mips|coprocessor 0}} control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most {{mips|CPUs}}. Due to its relative simplicity, the MIP32 instruction set is also the most common instruction set taught in computer architecture university courses.<br />
<br />
The latest MIPS32 revision is revision 5, which added a set of new memory-efficient operations for large memory footprint applications.<br />
<br />
== History ==<br />
The MIPS32 instruction set architecture was first published in 1999 by [[MIPS Technologies]] by it has demerged from [[Silicon Graphics]] in 1998. MIPS32 is largely a superset of the {{mips|MIPS II}} ISA.<br />
<br />
=== Release 2 ===<br />
Release 2 was first introduced in revision 1 of the MIPS32 ISA in 2002. Release 2 added 20 new instructions: {{mips|DI}}, {{mips|EHB}}, {{mips|EI}}, {{mips|EXT}}, {{mips|INS}}, {{mips|JALR.HB}}, {{mips|JR.HB}}, {{mips|MFHC1}}, {{mips|MFHC2}}, {{mips|MTHC1}}, {{mips|MTHC2}}, {{mips|RDHWR}}, {{mips|RDPGPR}}, {{mips|ROTR}}, {{mips|ROTRV}}, {{mips|SEB}}, {{mips|SEH}}, {{mips|SYNCI}}, {{mips|WRPGPR}}, and {{mips|WSBH}}. Release 2 also added support for 64-bit FPUs.<br />
<br />
=== Release 3 ===<br />
Release 3 was first introduced in revision 3 of the MIPS32 ISA in 2010. The release added the {{mips|JALX}} instruction.<br />
<br />
=== Release 4 ===<br />
Release 4 was skipped because MIPS Technologies was being auctioned off. Officially the reason was given as "Release 4 because the number four is considered by many to be inauspicious or unlucky".<ref>[http://withimagination.imgtec.com/index.php/mips-processors/continuing-evolution-of-the-mips-instruction-set-architecture#sthash.4uCPPXKz.dpuf The continuing evolution of the MIPS Instruction Set Architecture]</ref><br />
<br />
=== Release 5 ===<br />
Release 5 was announced in late 2012. The release added a new set of instructions called '''Enhanced Virtual Addressing''' (EVA) to allow more efficient use of memory of larger footprint kernels. The following EVA Load/Store instructions were added: {{mips|LBE}}, {{mips|LBUE}}, {{mips|LHE}}, {{mips|LHUE}}, {{mips|LWE}}, {{mips|SBE}}, {{mips|SHE}}, {{mips|SWE}}, {{mips|CACHEE}}, {{mips|PREFE}}, {{mips|LLE}}, {{mips|SCE}}, {{mips|LWLE}}, {{mips|LWRE}}, {{mips|SWLE}}, {{mips|SWRE}}.<br />
<br />
== Instructions list ==<br />
Below is a list of the MIPS32 Instruction Set<br />
<br />
* CPU Instructions<br />
** [[#Arithmetic instructions|Arithmetic Instructions]]<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Jump instructions|Jump Instructions]]<br />
** [[#Control instructions|Control Instructions]]<br />
** [[#Memory control instructions|Memory Control Instructions]]<br />
** [[#Logical instruction|Logical Instruction]]<br />
** [[#Insert/Extract instructions|Insert/Extract Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
** [[#Shift instructions|Shift Instructions]]<br />
** [[#Trap instructions|Trap Instructions]]<br />
* FPU Instructions<br />
** [[#Arithmetic instructions|Arithmetic Instructions]]<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Compare instructions|Compare Instructions]]<br />
** [[#Convert instructions|Convert Instructions]]<br />
** [[#Memory control instructions|Memory Control Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
* [[Coprocessor]] Instructions<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Execute instructions|Execute Instructions]]<br />
** [[#Memory control instructions|Memory control Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
* [[#Privileged instructions|Privileged Instructions]]<br />
* [[#EJTAG instructions|EJTAG Instructions]]<br />
<br />
=== Arithmetic instructions ===<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ADD}} || Add Word<br />
|-<br />
| {{mips|ADDI}} || Add Immediate Word<br />
|-<br />
| {{mips|ADDIU}} || Add Immediate Unsigned Word<br />
|-<br />
| {{mips|ADDU}} || Add Unsigned Word<br />
|-<br />
| {{mips|CLO}} || Count Leading Ones in Word<br />
|-<br />
| {{mips|CLZ}} || Count Leading Zeros in Word<br />
|-<br />
| {{mips|DIV}} || Divide Word<br />
|-<br />
| {{mips|DIVU}} || Divide Unsigned Word<br />
|-<br />
| {{mips|MADD}} || Multiply and Add Word to Hi, Lo<br />
|-<br />
| {{mips|MADDU}} || Multiply and Add Unsigned Word to Hi, Lo<br />
|-<br />
| {{mips|MSUB}} || Multiply and Subtract Word to Hi, Lo<br />
|-<br />
| {{mips|MSUBU}} || Multiply and Subtract Unsigned Word to Hi, Lo<br />
|-<br />
| {{mips|MUL}} || Multiply Word to GPR<br />
|-<br />
| {{mips|MULT}} || Multiply Word<br />
|-<br />
| {{mips|MULTU}} || Multiply Unsigned Word<br />
|-<br />
| {{mips|SEB}} || Sign-Extend Byte<br />
|-<br />
| {{mips|SEH}} || Sign-Extend Halfword<br />
|-<br />
| {{mips|SLT}} || Set on Less Than<br />
|-<br />
| {{mips|SLTI}} || Set on Less Than Immediate<br />
|-<br />
| {{mips|SLTIU}} || Set on Less Than Immediate Unsigned<br />
|-<br />
| {{mips|SLTU}} || Set on Less Than Unsigned<br />
|-<br />
| {{mips|SUB}} || Subtract Word<br />
|-<br />
| {{mips|SUBU}} || Subtract Unsigned Word<br />
|}<br />
<br />
=== Branch instructions ===<br />
Note that all the likely branches have been obsoleted; they will be removed in future revisions of the MIPS32 architecture. Software is strongly discouraged from using these instructions.<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|B}} || Unconditional Branch<br />
|-<br />
| {{mips|BAL}} || Branch and Link<br />
|-<br />
| {{mips|BEQ}} || Branch on Equal<br />
|-<br />
| {{mips|BGEZ}} || Branch on Greater Than or Equal to Zero<br />
|-<br />
| {{mips|BGEZAL}} || Branch on Greater Than or Equal to Zero and Link<br />
|-<br />
| {{mips|BGTZ}} || Branch on Greater Than Zero<br />
|-<br />
| {{mips|BLEZ}} || Branch on Less Than or Equal to Zero<br />
|-<br />
| {{mips|BLTZ}} || Branch on Less Than Zero<br />
|-<br />
| {{mips|BLTZAL}} || Branch on Less Than Zero and Link<br />
|-<br />
| {{mips|BNE}} || Branch on Not Equal<br />
|-<br />
| <strike>{{mips|BEQL}}</strike> || Branch on Equal Likely<br />
|-<br />
| <strike>{{mips|BGEZALL}}</strike> || Branch on Greater Than or Equal to Zero and Link Likely<br />
|-<br />
| <strike>{{mips|BGEZL}}</strike> || Branch on Greater Than or Equal to Zero Likely<br />
|-<br />
| <strike>{{mips|BGTZL}}</strike> || Branch on Greater Than Zero Likely<br />
|-<br />
| <strike>{{mips|BLEZL}}</strike> || Branch on Less Than or Equal to Zero Likely<br />
|-<br />
| <strike>{{mips|BLTZALL}}</strike> || Branch on Less Than Zero and Link Likely<br />
|-<br />
| <strike>{{mips|BLTZL}}</strike> || Branch on Less Than Zero Likely<br />
|-<br />
| <strike>{{mips|BNEL}}</strike> || Branch on Not Equal Likely<br />
|}<br />
<br />
=== Jump instructions ===<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|J}} || Jump<br />
|-<br />
| {{mips|JAL}} || Jump and Link<br />
|-<br />
| {{mips|JALR}} || Jump and Link Register<br />
|-<br />
| [[JALR.HB - MIPS|JALR.HB ]]|| Jump and Link Register with Hazard Barrier<br />
|-<br />
| {{mips|JALX}} || Jump and Link Exchange<br />
|-<br />
| {{mips|JR}} || Jump Register<br />
|-<br />
| {{mips|JR.HB}} || Jump Register with Hazard Barrier<br />
|}<br />
<br />
=== Control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|EHB}} || Execution Hazard Barrier<br />
|-<br />
| {{mips|NOP}} || No Operation<br />
|-<br />
| {{mips|PAUSE}} || Wait for LLBit to Clear<br />
|-<br />
| {{mips|SSNOP}} || Superscalar No Operation<br />
|}<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|LB}} || Load Byte<br />
|-<br />
| {{mips|LBE}} || Load Byte EVA<br />
|-<br />
| {{mips|LBU}} || Load Byte Unsigned<br />
|-<br />
| {{mips|LBUE}} || Load Byte Unsigned EVA<br />
|-<br />
| {{mips|LH}} || Load Halfword<br />
|-<br />
| {{mips|LHE}} || Load Halfword EVA<br />
|-<br />
| {{mips|LHU}} || Load Halfword Unsigned<br />
|-<br />
| {{mips|LHUE}} || Load Halfword Unsigned EVA<br />
|-<br />
| {{mips|LL}} || Load Linked Word<br />
|-<br />
| {{mips|LLE}} || Load Linked Word-EVA<br />
|-<br />
| {{mips|LW}} || Load Word<br />
|-<br />
| {{mips|LWE}} || Load Word EVA<br />
|-<br />
| {{mips|LWL}} || Load Word Left<br />
|-<br />
| {{mips|LWLE}} || Load Word Left EVA<br />
|-<br />
| {{mips|LWR}} || Load Word Right<br />
|-<br />
| {{mips|LWRE}} || Load Word Right EVA<br />
|-<br />
| {{mips|PREF}} || Prefetch<br />
|-<br />
| {{mips|PREFE}} || Prefetch-EVA<br />
|-<br />
| {{mips|SB}} || Store Byte<br />
|-<br />
| {{mips|SBE}} || Store Byte EVA<br />
|-<br />
| {{mips|SC}} || Store Conditional Word<br />
|-<br />
| {{mips|SCE}} || Store Conditional Word EVA<br />
|-<br />
| {{mips|SH}} || Store Halfword<br />
|-<br />
| {{mips|SHE}} || Store Halfword EVA<br />
|-<br />
| {{mips|SW}} || Store Word<br />
|-<br />
| {{mips|SWE}} || Store Word EVA<br />
|-<br />
| {{mips|SWL}} || Store Word Left<br />
|-<br />
| {{mips|SWLE}} || Store Word Left EVA<br />
|-<br />
| {{mips|SWR}} || Store Word Right<br />
|-<br />
| {{mips|SWRE}} || Store Word Right EVA<br />
|-<br />
| {{mips|SYNC}} || Synchronize Shared Memory<br />
|-<br />
| {{mips|SYNCI}} || Synchronize Caches to Make Instruction Writes Effective<br />
|}<br />
<br />
=== Logical instruction ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|AND}} || And<br />
|-<br />
| {{mips|ANDI}} || And Immediate<br />
|-<br />
| {{mips|LUI}} || Load Upper Immediate<br />
|-<br />
| {{mips|NOR}} || Not Or<br />
|-<br />
| {{mips|OR}} || Or<br />
|-<br />
| {{mips|ORI}} || Or Immediate<br />
|-<br />
| {{mips|XOR}} || Exclusive Or<br />
|-<br />
| {{mips|XORI}} || Exclusive Or Immediate<br />
|}<br />
<br />
=== Insert/Extract instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|EXT}} || Extract Bit Field<br />
|-<br />
| {{mips|INS}} || Insert Bit Field<br />
|-<br />
| {{mips|WSBH}} || Word Swap Bytes Within Halfwords<br />
|}<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|MFHI}} || Move From HI Register<br />
|-<br />
| {{mips|MFLO}} || Move From LO Register<br />
|-<br />
| {{mips|MOVF}} || Move Conditional on Floating Point False<br />
|-<br />
| {{mips|MOVN}} || Move Conditional on Not Zero<br />
|-<br />
| {{mips|MOVT}} || Move Conditional on Floating Point True<br />
|-<br />
| {{mips|MOVZ}} || Move Conditional on Zero<br />
|-<br />
| {{mips|MTHI}} || Move To HI Register<br />
|-<br />
| {{mips|MTLO}} || Move To LO Register<br />
|-<br />
| {{mips|RDHWR}} || Read Hardware Register<br />
|}<br />
<br />
=== Shift instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ROTR}} || Rotate Word Right<br />
|-<br />
| {{mips|ROTRV}} || Rotate Word Right Variable<br />
|-<br />
| {{mips|SLL}} || Shift Word Left Logical<br />
|-<br />
| {{mips|SLLV}} || Shift Word Left Logical Variable<br />
|-<br />
| {{mips|SRA}} || Shift Word Right Arithmetic<br />
|-<br />
| {{mips|SRAV}} || Shift Word Right Arithmetic Variable<br />
|-<br />
| {{mips|SRL}} || Shift Word Right Logical<br />
|-<br />
| {{mips|SRLV}} || Shift Word Right Logical Variable<br />
|}<br />
<br />
=== Trap instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BREAK}} || Breakpoint<br />
|-<br />
| {{mips|SYSCALL}} || System Call<br />
|-<br />
| {{mips|TEQ}} || Trap if Equal<br />
|-<br />
| {{mips|TEQI}} || Trap if Equal Immediate<br />
|-<br />
| {{mips|TGE}} || Trap if Greater or Equal<br />
|-<br />
| {{mips|TGEI}} || Trap if Greater of Equal Immediate<br />
|-<br />
| {{mips|TGEIU}} || Trap if Greater or Equal Immediate Unsigned<br />
|-<br />
| {{mips|TGEU}} || Trap if Greater or Equal Unsigned<br />
|-<br />
| {{mips|TLT}} || Trap if Less Than<br />
|-<br />
| {{mips|TLTI}} || Trap if Less Than Immediate<br />
|-<br />
| {{mips|TLTIU}} || Trap if Less Than Immediate Unsigned<br />
|-<br />
| {{mips|TLTU}} || Trap if Less Than Unsigned<br />
|-<br />
| {{mips|TNE}} || Trap if Not Equal<br />
|-<br />
| {{mips|TNEI}} || Trap if Not Equal Immediate<br />
|}<br />
<br />
<br />
== FPU instructions ==<br />
<br />
=== Arithmetic instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ABS.fmt}} || Floating Point Absolute Value<br />
|-<br />
| {{mips|ADD.fmt}} || Floating Point Add<br />
|-<br />
| {{mips|DIV.fmt}} || Floating Point Divide<br />
|-<br />
| {{mips|MADD.fmt}} || Floating Point Multiply Add<br />
|-<br />
| {{mips|MSUB.fmt}} || Floating Point Multiply Subtract<br />
|-<br />
| {{mips|MUL.fmt}} || Floating Point Multiply<br />
|-<br />
| {{mips|NEG.fmt}} || Floating Point Negate<br />
|-<br />
| {{mips|NMADD.fmt}} || Floating Point Negative Multiply Add<br />
|-<br />
| {{mips|NMSUB.fmt}} || Floating Point Negative Multiply Subtract<br />
|-<br />
| {{mips|RECIP.fmt}} || Reciprocal Approximation<br />
|-<br />
| {{mips|RSQRT.fmt}} || Reciprocal Square Root Approximation<br />
|-<br />
| {{mips|SQRT.fmt}} || Floating Point Square Root<br />
|-<br />
| {{mips|SUB.fmt}} || Floating Point Subtract<br />
|}<br />
<br />
<br />
=== Branch instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BC1F}} || Branch on FP False<br />
|-<br />
| {{mips|BC1T}} || Branch on FP True<br />
|-<br />
| <strike>{{mips|BC1FL}}</strike> || Branch on FP False Likely<br />
|-<br />
| <strike>{{mips|BC1TL}}</strike> || Branch on FP True Likely<br />
|}<br />
<br />
=== Compare instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|C.cond.fmt}} || Floating Point Compare<br />
|}<br />
<br />
=== Convert instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ALNV.PS}} || Floating Point Align Variable<br />
|-<br />
| {{mips|CEIL.L.fmt}} || Floating Point Ceiling Convert to Long Fixed Point<br />
|-<br />
| {{mips|CEIL.W.fmt}} || Floating Point Ceiling Convert to Word Fixed Point<br />
|-<br />
| {{mips|CVT.D.fmt}} || Floating Point Convert to Double Floating Point<br />
|-<br />
| {{mips|CVT.L.fmt}} || Floating Point Convert to Long Fixed Point<br />
|-<br />
| {{mips|CVT.PS.S}} || Floating Point Convert Pair to Paired Single<br />
|-<br />
| {{mips|CVT.S.PL}} || Floating Point Convert Pair Lower to Single Floating Point<br />
|-<br />
| {{mips|CVT.S.PU}} || Floating Point Convert Pair Upper to Single Floating Point<br />
|-<br />
| {{mips|CVT.S.fmt}} || Floating Point Convert to Single Floating Point<br />
|-<br />
| {{mips|CVT.W.fmt}} || Floating Point Convert to Word Fixed Point<br />
|-<br />
| {{mips|FLOOR.L.fmt}} || Floating Point Floor Convert to Long Fixed Point<br />
|-<br />
| {{mips|FLOOR.W.fmt}} || Floating Point Floor Convert to Word Fixed Point<br />
|-<br />
| {{mips|PLL.PS}} || Pair Lower Lower<br />
|-<br />
| {{mips|PLU.PS}} || Pair Lower Upper<br />
|-<br />
| {{mips|PUL.PS}} || Pair Upper Lower<br />
|-<br />
| {{mips|PUU.PS}} || Pair Upper Upper<br />
|-<br />
| {{mips|ROUND.L.fmt}} || Floating Point Round to Long Fixed Point<br />
|-<br />
| {{mips|ROUND.W.fmt}} || Floating Point Round to Word Fixed Point<br />
|-<br />
| {{mips|TRUNC.L.fmt}} || Floating Point Truncate to Long Fixed Point<br />
|-<br />
| {{mips|TRUNC.W.fmt}} || Floating Point Truncate to Word Fixed Point<br />
|}<br />
<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|LDC1}} || Load Doubleword to Floating Point<br />
|-<br />
| {{mips|LDXC1}} || Load Doubleword Indexed to Floating Point<br />
|-<br />
| {{mips|LUXC1}} || Load Doubleword Indexed Unaligned to Floating Point<br />
|-<br />
| {{mips|LWC1}} || Load Word to Floating Point<br />
|-<br />
| {{mips|LWXC1}} || Load Word Indexed to Floating Point<br />
|-<br />
| {{mips|PREFX}} || Prefetch Indexed<br />
|-<br />
| {{mips|SDC1}} || Store Doubleword from Floating Point<br />
|-<br />
| {{mips|SDXC1}} || Store Doubleword Indexed from Floating Point<br />
|-<br />
| {{mips|SUXC1}} || Store Doubleword Indexed Unaligned from Floating Point<br />
|-<br />
| {{mips|SWC1}} || Store Word from Floating Point<br />
|-<br />
| {{mips|SWXC1}} || Store Word Indexed from Floating Point<br />
|}<br />
<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CFC1}} || Move Control Word from Floating Point<br />
|-<br />
| {{mips|CTC1}} || Move Control Word to Floating Point<br />
|-<br />
| {{mips|MFC1}} || Move Word from Floating Point<br />
|-<br />
| {{mips|MFHC1}} || Move Word from High Half of Floating Point Register<br />
|-<br />
| {{mips|MOV.fmt}} || Floating Point Move<br />
|-<br />
| {{mips|MOVF.fmt}} || Floating Point Move Conditional on Floating Point False<br />
|-<br />
| {{mips|MOVN.fmt}} || Floating Point Move Conditional on Not Zero<br />
|-<br />
| {{mips|MOVT.fmt}} || Floating Point Move Conditional on Floating Point True<br />
|-<br />
| {{mips|MOVZ.fmt}} || Floating Point Move Conditional on Zero<br />
|-<br />
| {{mips|MTC1}} || Move Word to Floating Point<br />
|-<br />
| {{mips|MTHC1}} || Move Word to High Half of Floating Point Register<br />
|}<br />
<br />
== Coprocessor instructions ==<br />
<br />
=== Branch instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BC2F}} || Branch on COP2 False<br />
|-<br />
| {{mips|BC2T}} || Branch on COP2 True<br />
|-<br />
| <strike>{{mips|BC2FL}}</strike> || Branch on COP2 False Likely<br />
|-<br />
| <strike>{{mips|BC2TL}}</strike> || Branch on COP2 True Likely<br />
|}<br />
<br />
<br />
=== Execute instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|COP2}} || Coprocessor Operation to Coprocessor 2<br />
|}<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|DC2}} || Load Doubleword to Coprocessor 2<br />
|-<br />
| {{mips|LWC2}} || Load Word to Coprocessor 2<br />
|-<br />
| {{mips|SDC2}} || Store Doubleword from Coprocessor 2<br />
|-<br />
| {{mips|SWC2}} || Store Word from Coprocessor 2<br />
|}<br />
<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CFC2}} || Move Control Word from Coprocessor 2<br />
|-<br />
| {{mips|CTC2}} || Move Control Word to Coprocessor 2<br />
|-<br />
| {{mips|MFC2}} || Move Word from Coprocessor 2<br />
|-<br />
| {{mips|MFHC2}} || Move Word from High Half of Coprocessor 2 Register<br />
|-<br />
| {{mips|MTC2}} || Move Word to Coprocessor 2<br />
|-<br />
| {{mips|MTHC2}} || Move Word to High Half of Coprocessor 2 Register<br />
|}<br />
<br />
<br />
== Privileged instructions ==<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CACHE}} || Perform Cache Operation<br />
|-<br />
| {{mips|CACHEE}} || Perform Cache Operation EVA<br />
|-<br />
| {{mips|DI}} || Disable Interrupts<br />
|-<br />
| {{mips|EI}} || Enable Interrupts<br />
|-<br />
| {{mips|ERET}} || Exception Return<br />
|-<br />
| {{mips|MFC0}} || Move from {{mips|Coprocessor 0}}<br />
|-<br />
| {{mips|MTC0}} || Move to {{mips|Coprocessor 0}}<br />
|-<br />
| {{mips|RDPGPR}} || Read GPR from Previous Shadow Set<br />
|-<br />
| {{mips|TLBP}} || Probe TLB for Matching Entry<br />
|-<br />
| {{mips|TLBR}} || Read Indexed TLB Entry<br />
|-<br />
| {{mips|TLBWI}} || Write Indexed TLB Entry<br />
|-<br />
| {{mips|TLBWR}} || Write Random TLB Entry<br />
|-<br />
| {{mips|WAIT}} || Enter Standby Mode<br />
|-<br />
| {{mips|WRPGPR}} || Write GPR to Previous Shadow Set<br />
|}<br />
<br />
== EJTAG instructions ==<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|DERET}} ||Debug Exception Return<br />
|-<br />
| {{mips|SDBBP}} || Software Debug Breakpoint<br />
|}<br />
<br />
== References ==<br />
{{reflist|30em}}<br />
<br />
[[Category:Assembly language]]<br />
[[Category:MIPS]]<br />
[[Category:MIPS32]]<br />
[[Category:RISC instruction set]]<br />
[[Category:Instruction set architecture]]</div>
77.243.191.41
https://en.wikichip.org/w/index.php?title=mips/mips32_instruction_set&diff=94362
mips/mips32 instruction set
2019-11-09T12:20:35Z
<p>77.243.191.41: Fixed verb</p>
<hr />
<div>{{mips title|MIPS32 Instruction Set}}<br />
{{ISA|<br />
|name = MIPS32<br />
|designer = [[MIPS Technologies, Inc.]]<br />
|bits = 32-bits<br />
|introduced = 1999<br />
|version = Revision 5.3<br />
|design = RISC<br />
|type = Register-Register<br />
|encoding = Fixed-length<br />
|branching = Condition Register<br />
|endianness = Bi-endian<br />
|extensions = {{mips|SPECIAL2}}, {{mips|COP2}}, {{mips|LWC2}}, {{mips|SWC2}}, {{mips|LDC2}}, {{mips|SDC2}}<br />
|application = {{mips|MIPS16e}}, {{mips|MCU}}, {{mips|SmartMIPS}}<br />
|multimedia = {{mips|MIPS-3D}}<br />
|gpr = 32<br />
|fpr = 32<br />
|spr = {{mips|PRId register|PRId}}<br />
}}<br />
<br />
The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the {{mips|MIPS64 Instruction Set}} which includes 64-bit instructions. The MIP32 standard included {{mips|coprocessor 0}} control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most {{mips|CPUs}}. Due to its relative simplicity, the MIP32 instruction set is also the most common instruction set taught in computer architecture university courses.<br />
<br />
The latest MIPS32 revision is revision 5, which added a set of new memory-efficient operations for large memory footprint applications.<br />
<br />
== History ==<br />
The MIPS32 instruction set architecture was first published in 1999 by [[MIPS Technologies]] by it has demerged from [[Silicon Graphics]] in 1998. MIPS32 is largely a superset of the {{mips|MIPS II}} ISA.<br />
<br />
=== Release 2 ===<br />
Release 2 was first introduced in revision 1 of the MIPS32 ISA in 2002. Release 2 added 20 new instructions: {{mips|DI}}, {{mips|EHB}}, {{mips|EI}}, {{mips|EXT}}, {{mips|INS}}, {{mips|JALR.HB}}, {{mips|JR.HB}}, {{mips|MFHC1}}, {{mips|MFHC2}}, {{mips|MTHC1}}, {{mips|MTHC2}}, {{mips|RDHWR}}, {{mips|RDPGPR}}, {{mips|ROTR}}, {{mips|ROTRV}}, {{mips|SEB}}, {{mips|SEH}}, {{mips|SYNCI}}, {{mips|WRPGPR}}, and {{mips|WSBH}}. Release 2 also added support for 64-bit FPUs.<br />
<br />
=== Release 3 ===<br />
Release 3 was first introduced in revision 3 of the MIPS32 ISA in 2010. The release added the {{mips|JALX}} instruction.<br />
<br />
=== Release 4 ===<br />
Release 4 was skipped because MIPS Technologies was being auctioned off. Officially the reason was given as "Release 4 because the number four is considered by many to be inauspicious or unlucky".<ref>[http://withimagination.imgtec.com/index.php/mips-processors/continuing-evolution-of-the-mips-instruction-set-architecture#sthash.4uCPPXKz.dpuf The continuing evolution of the MIPS Instruction Set Architecture]</ref><br />
<br />
=== Release 5 ===<br />
Release 5 was announced in late 2012. The release added a new set of instructions called '''Enhanced Virtual Addressing''' (EVA) to allow more efficient use of memory of larger footprint kernels. The following EVA Load/Store instructions were added: {{mips|LBE}}, {{mips|LBUE}}, {{mips|LHE}}, {{mips|LHUE}}, {{mips|LWE}}, {{mips|SBE}}, {{mips|SHE}}, {{mips|SWE}}, {{mips|CACHEE}}, {{mips|PREFE}}, {{mips|LLE}}, {{mips|SCE}}, {{mips|LWLE}}, {{mips|LWRE}}, {{mips|SWLE}}, {{mips|SWRE}}.<br />
<br />
== Instructions list ==<br />
Below is a list of the MIPS32 Instruction Set<br />
<br />
* CPU Instructions<br />
** [[#Arithmetic instructions|Arithmetic Instructions]]<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Jump instructions|Jump Instructions]]<br />
** [[#Control instructions|Control Instructions]]<br />
** [[#Memory control instructions|Memory Control Instructions]]<br />
** [[#Logical instruction|Logical Instruction]]<br />
** [[#Insert/Extract instructions|Insert/Extract Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
** [[#Shift instructions|Shift Instructions]]<br />
** [[#Trap instructions|Trap Instructions]]<br />
* FPU Instructions<br />
** [[#Arithmetic instructions|Arithmetic Instructions]]<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Compare instructions|Compare Instructions]]<br />
** [[#Convert instructions|Convert Instructions]]<br />
** [[#Memory control instructions|Memory Control Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
* [[Coprocessor]] Instructions<br />
** [[#Branch instructions|Branch Instructions]]<br />
** [[#Execute instructions|Execute Instructions]]<br />
** [[#Memory control instructions|Memory control Instructions]]<br />
** [[#Move instructions|Move Instructions]]<br />
* [[#Privileged instructions|Privileged Instructions]]<br />
* [[#EJTAG instructions|EJTAG Instructions]]<br />
<br />
=== Arithmetic instructions ===<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ADD}} || Add Word<br />
|-<br />
| {{mips|ADDI}} || Add Immediate Word<br />
|-<br />
| {{mips|ADDIU}} || Add Immediate Unsigned Word<br />
|-<br />
| {{mips|ADDU}} || Add Unsigned Word<br />
|-<br />
| {{mips|CLO}} || Count Leading Ones in Word<br />
|-<br />
| {{mips|CLZ}} || Count Leading Zeros in Word<br />
|-<br />
| {{mips|DIV}} || Divide Word<br />
|-<br />
| {{mips|DIVU}} || Divide Unsigned Word<br />
|-<br />
| {{mips|MADD}} || Multiply and Add Word to Hi, Lo<br />
|-<br />
| {{mips|MADDU}} || Multiply and Add Unsigned Word to Hi, Lo<br />
|-<br />
| {{mips|MSUB}} || Multiply and Subtract Word to Hi, Lo<br />
|-<br />
| {{mips|MSUBU}} || Multiply and Subtract Unsigned Word to Hi, Lo<br />
|-<br />
| {{mips|MUL}} || Multiply Word to GPR<br />
|-<br />
| {{mips|MULT}} || Multiply Word<br />
|-<br />
| {{mips|MULTU}} || Multiply Unsigned Word<br />
|-<br />
| {{mips|SEB}} || Sign-Extend Byte<br />
|-<br />
| {{mips|SEH}} || Sign-Extend Halftword<br />
|-<br />
| {{mips|SLT}} || Set on Less Than<br />
|-<br />
| {{mips|SLTI}} || Set on Less Than Immediate<br />
|-<br />
| {{mips|SLTIU}} || Set on Less Than Immediate Unsigned<br />
|-<br />
| {{mips|SLTU}} || Set on Less Than Unsigned<br />
|-<br />
| {{mips|SUB}} || Subtract Word<br />
|-<br />
| {{mips|SUBU}} || Subtract Unsigned Word<br />
|}<br />
<br />
=== Branch instructions ===<br />
Note that all the likely branches have been obsoleted; they will be removed in future revisions of the MIPS32 architecture. Software is strongly discouraged from using these instructions.<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|B}} || Unconditional Branch<br />
|-<br />
| {{mips|BAL}} || Branch and Link<br />
|-<br />
| {{mips|BEQ}} || Branch on Equal<br />
|-<br />
| {{mips|BGEZ}} || Branch on Greater Than or Equal to Zero<br />
|-<br />
| {{mips|BGEZAL}} || Branch on Greater Than or Equal to Zero and Link<br />
|-<br />
| {{mips|BGTZ}} || Branch on Greater Than Zero<br />
|-<br />
| {{mips|BLEZ}} || Branch on Less Than or Equal to Zero<br />
|-<br />
| {{mips|BLTZ}} || Branch on Less Than Zero<br />
|-<br />
| {{mips|BLTZAL}} || Branch on Less Than Zero and Link<br />
|-<br />
| {{mips|BNE}} || Branch on Not Equal<br />
|-<br />
| <strike>{{mips|BEQL}}</strike> || Branch on Equal Likely<br />
|-<br />
| <strike>{{mips|BGEZALL}}</strike> || Branch on Greater Than or Equal to Zero and Link Likely<br />
|-<br />
| <strike>{{mips|BGEZL}}</strike> || Branch on Greater Than or Equal to Zero Likely<br />
|-<br />
| <strike>{{mips|BGTZL}}</strike> || Branch on Greater Than Zero Likely<br />
|-<br />
| <strike>{{mips|BLEZL}}</strike> || Branch on Less Than or Equal to Zero Likely<br />
|-<br />
| <strike>{{mips|BLTZALL}}</strike> || Branch on Less Than Zero and Link Likely<br />
|-<br />
| <strike>{{mips|BLTZL}}</strike> || Branch on Less Than Zero Likely<br />
|-<br />
| <strike>{{mips|BNEL}}</strike> || Branch on Not Equal Likely<br />
|}<br />
<br />
=== Jump instructions ===<br />
<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|J}} || Jump<br />
|-<br />
| {{mips|JAL}} || Jump and Link<br />
|-<br />
| {{mips|JALR}} || Jump and Link Register<br />
|-<br />
| [[JALR.HB - MIPS|JALR.HB ]]|| Jump and Link Register with Hazard Barrier<br />
|-<br />
| {{mips|JALX}} || Jump and Link Exchange<br />
|-<br />
| {{mips|JR}} || Jump Register<br />
|-<br />
| {{mips|JR.HB}} || Jump Register with Hazard Barrier<br />
|}<br />
<br />
=== Control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|EHB}} || Execution Hazard Barrier<br />
|-<br />
| {{mips|NOP}} || No Operation<br />
|-<br />
| {{mips|PAUSE}} || Wait for LLBit to Clear<br />
|-<br />
| {{mips|SSNOP}} || Superscalar No Operation<br />
|}<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|LB}} || Load Byte<br />
|-<br />
| {{mips|LBE}} || Load Byte EVA<br />
|-<br />
| {{mips|LBU}} || Load Byte Unsigned<br />
|-<br />
| {{mips|LBUE}} || Load Byte Unsigned EVA<br />
|-<br />
| {{mips|LH}} || Load Halfword<br />
|-<br />
| {{mips|LHE}} || Load Halfword EVA<br />
|-<br />
| {{mips|LHU}} || Load Halfword Unsigned<br />
|-<br />
| {{mips|LHUE}} || Load Halfword Unsigned EVA<br />
|-<br />
| {{mips|LL}} || Load Linked Word<br />
|-<br />
| {{mips|LLE}} || Load Linked Word-EVA<br />
|-<br />
| {{mips|LW}} || Load Word<br />
|-<br />
| {{mips|LWE}} || Load Word EVA<br />
|-<br />
| {{mips|LWL}} || Load Word Left<br />
|-<br />
| {{mips|LWLE}} || Load Word Left EVA<br />
|-<br />
| {{mips|LWR}} || Load Word Right<br />
|-<br />
| {{mips|LWRE}} || Load Word Right EVA<br />
|-<br />
| {{mips|PREF}} || Prefetch<br />
|-<br />
| {{mips|PREFE}} || Prefetch-EVA<br />
|-<br />
| {{mips|SB}} || Store Byte<br />
|-<br />
| {{mips|SBE}} || Store Byte EVA<br />
|-<br />
| {{mips|SC}} || Store Conditional Word<br />
|-<br />
| {{mips|SCE}} || Store Conditional Word EVA<br />
|-<br />
| {{mips|SH}} || Store Halfword<br />
|-<br />
| {{mips|SHE}} || Store Halfword EVA<br />
|-<br />
| {{mips|SW}} || Store Word<br />
|-<br />
| {{mips|SWE}} || Store Word EVA<br />
|-<br />
| {{mips|SWL}} || Store Word Left<br />
|-<br />
| {{mips|SWLE}} || Store Word Left EVA<br />
|-<br />
| {{mips|SWR}} || Store Word Right<br />
|-<br />
| {{mips|SWRE}} || Store Word Right EVA<br />
|-<br />
| {{mips|SYNC}} || Synchronize Shared Memory<br />
|-<br />
| {{mips|SYNCI}} || Synchronize Caches to Make Instruction Writes Effective<br />
|}<br />
<br />
=== Logical instruction ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|AND}} || And<br />
|-<br />
| {{mips|ANDI}} || And Immediate<br />
|-<br />
| {{mips|LUI}} || Load Upper Immediate<br />
|-<br />
| {{mips|NOR}} || Not Or<br />
|-<br />
| {{mips|OR}} || Or<br />
|-<br />
| {{mips|ORI}} || Or Immediate<br />
|-<br />
| {{mips|XOR}} || Exclusive Or<br />
|-<br />
| {{mips|XORI}} || Exclusive Or Immediate<br />
|}<br />
<br />
=== Insert/Extract instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|EXT}} || Extract Bit Field<br />
|-<br />
| {{mips|INS}} || Insert Bit Field<br />
|-<br />
| {{mips|WSBH}} || Word Swap Bytes Within Halfwords<br />
|}<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|MFHI}} || Move From HI Register<br />
|-<br />
| {{mips|MFLO}} || Move From LO Register<br />
|-<br />
| {{mips|MOVF}} || Move Conditional on Floating Point False<br />
|-<br />
| {{mips|MOVN}} || Move Conditional on Not Zero<br />
|-<br />
| {{mips|MOVT}} || Move Conditional on Floating Point True<br />
|-<br />
| {{mips|MOVZ}} || Move Conditional on Zero<br />
|-<br />
| {{mips|MTHI}} || Move To HI Register<br />
|-<br />
| {{mips|MTLO}} || Move To LO Register<br />
|-<br />
| {{mips|RDHWR}} || Read Hardware Register<br />
|}<br />
<br />
=== Shift instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ROTR}} || Rotate Word Right<br />
|-<br />
| {{mips|ROTRV}} || Rotate Word Right Variable<br />
|-<br />
| {{mips|SLL}} || Shift Word Left Logical<br />
|-<br />
| {{mips|SLLV}} || Shift Word Left Logical Variable<br />
|-<br />
| {{mips|SRA}} || Shift Word Right Arithmetic<br />
|-<br />
| {{mips|SRAV}} || Shift Word Right Arithmetic Variable<br />
|-<br />
| {{mips|SRL}} || Shift Word Right Logical<br />
|-<br />
| {{mips|SRLV}} || Shift Word Right Logical Variable<br />
|}<br />
<br />
=== Trap instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BREAK}} || Breakpoint<br />
|-<br />
| {{mips|SYSCALL}} || System Call<br />
|-<br />
| {{mips|TEQ}} || Trap if Equal<br />
|-<br />
| {{mips|TEQI}} || Trap if Equal Immediate<br />
|-<br />
| {{mips|TGE}} || Trap if Greater or Equal<br />
|-<br />
| {{mips|TGEI}} || Trap if Greater of Equal Immediate<br />
|-<br />
| {{mips|TGEIU}} || Trap if Greater or Equal Immediate Unsigned<br />
|-<br />
| {{mips|TGEU}} || Trap if Greater or Equal Unsigned<br />
|-<br />
| {{mips|TLT}} || Trap if Less Than<br />
|-<br />
| {{mips|TLTI}} || Trap if Less Than Immediate<br />
|-<br />
| {{mips|TLTIU}} || Trap if Less Than Immediate Unsigned<br />
|-<br />
| {{mips|TLTU}} || Trap if Less Than Unsigned<br />
|-<br />
| {{mips|TNE}} || Trap if Not Equal<br />
|-<br />
| {{mips|TNEI}} || Trap if Not Equal Immediate<br />
|}<br />
<br />
<br />
== FPU instructions ==<br />
<br />
=== Arithmetic instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ABS.fmt}} || Floating Point Absolute Value<br />
|-<br />
| {{mips|ADD.fmt}} || Floating Point Add<br />
|-<br />
| {{mips|DIV.fmt}} || Floating Point Divide<br />
|-<br />
| {{mips|MADD.fmt}} || Floating Point Multiply Add<br />
|-<br />
| {{mips|MSUB.fmt}} || Floating Point Multiply Subtract<br />
|-<br />
| {{mips|MUL.fmt}} || Floating Point Multiply<br />
|-<br />
| {{mips|NEG.fmt}} || Floating Point Negate<br />
|-<br />
| {{mips|NMADD.fmt}} || Floating Point Negative Multiply Add<br />
|-<br />
| {{mips|NMSUB.fmt}} || Floating Point Negative Multiply Subtract<br />
|-<br />
| {{mips|RECIP.fmt}} || Reciprocal Approximation<br />
|-<br />
| {{mips|RSQRT.fmt}} || Reciprocal Square Root Approximation<br />
|-<br />
| {{mips|SQRT.fmt}} || Floating Point Square Root<br />
|-<br />
| {{mips|SUB.fmt}} || Floating Point Subtract<br />
|}<br />
<br />
<br />
=== Branch instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BC1F}} || Branch on FP False<br />
|-<br />
| {{mips|BC1T}} || Branch on FP True<br />
|-<br />
| <strike>{{mips|BC1FL}}</strike> || Branch on FP False Likely<br />
|-<br />
| <strike>{{mips|BC1TL}}</strike> || Branch on FP True Likely<br />
|}<br />
<br />
=== Compare instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|C.cond.fmt}} || Floating Point Compare<br />
|}<br />
<br />
=== Convert instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|ALNV.PS}} || Floating Point Align Variable<br />
|-<br />
| {{mips|CEIL.L.fmt}} || Floating Point Ceiling Convert to Long Fixed Point<br />
|-<br />
| {{mips|CEIL.W.fmt}} || Floating Point Ceiling Convert to Word Fixed Point<br />
|-<br />
| {{mips|CVT.D.fmt}} || Floating Point Convert to Double Floating Point<br />
|-<br />
| {{mips|CVT.L.fmt}} || Floating Point Convert to Long Fixed Point<br />
|-<br />
| {{mips|CVT.PS.S}} || Floating Point Convert Pair to Paired Single<br />
|-<br />
| {{mips|CVT.S.PL}} || Floating Point Convert Pair Lower to Single Floating Point<br />
|-<br />
| {{mips|CVT.S.PU}} || Floating Point Convert Pair Upper to Single Floating Point<br />
|-<br />
| {{mips|CVT.S.fmt}} || Floating Point Convert to Single Floating Point<br />
|-<br />
| {{mips|CVT.W.fmt}} || Floating Point Convert to Word Fixed Point<br />
|-<br />
| {{mips|FLOOR.L.fmt}} || Floating Point Floor Convert to Long Fixed Point<br />
|-<br />
| {{mips|FLOOR.W.fmt}} || Floating Point Floor Convert to Word Fixed Point<br />
|-<br />
| {{mips|PLL.PS}} || Pair Lower Lower<br />
|-<br />
| {{mips|PLU.PS}} || Pair Lower Upper<br />
|-<br />
| {{mips|PUL.PS}} || Pair Upper Lower<br />
|-<br />
| {{mips|PUU.PS}} || Pair Upper Upper<br />
|-<br />
| {{mips|ROUND.L.fmt}} || Floating Point Round to Long Fixed Point<br />
|-<br />
| {{mips|ROUND.W.fmt}} || Floating Point Round to Word Fixed Point<br />
|-<br />
| {{mips|TRUNC.L.fmt}} || Floating Point Truncate to Long Fixed Point<br />
|-<br />
| {{mips|TRUNC.W.fmt}} || Floating Point Truncate to Word Fixed Point<br />
|}<br />
<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|LDC1}} || Load Doubleword to Floating Point<br />
|-<br />
| {{mips|LDXC1}} || Load Doubleword Indexed to Floating Point<br />
|-<br />
| {{mips|LUXC1}} || Load Doubleword Indexed Unaligned to Floating Point<br />
|-<br />
| {{mips|LWC1}} || Load Word to Floating Point<br />
|-<br />
| {{mips|LWXC1}} || Load Word Indexed to Floating Point<br />
|-<br />
| {{mips|PREFX}} || Prefetch Indexed<br />
|-<br />
| {{mips|SDC1}} || Store Doubleword from Floating Point<br />
|-<br />
| {{mips|SDXC1}} || Store Doubleword Indexed from Floating Point<br />
|-<br />
| {{mips|SUXC1}} || Store Doubleword Indexed Unaligned from Floating Point<br />
|-<br />
| {{mips|SWC1}} || Store Word from Floating Point<br />
|-<br />
| {{mips|SWXC1}} || Store Word Indexed from Floating Point<br />
|}<br />
<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CFC1}} || Move Control Word from Floating Point<br />
|-<br />
| {{mips|CTC1}} || Move Control Word to Floating Point<br />
|-<br />
| {{mips|MFC1}} || Move Word from Floating Point<br />
|-<br />
| {{mips|MFHC1}} || Move Word from High Half of Floating Point Register<br />
|-<br />
| {{mips|MOV.fmt}} || Floating Point Move<br />
|-<br />
| {{mips|MOVF.fmt}} || Floating Point Move Conditional on Floating Point False<br />
|-<br />
| {{mips|MOVN.fmt}} || Floating Point Move Conditional on Not Zero<br />
|-<br />
| {{mips|MOVT.fmt}} || Floating Point Move Conditional on Floating Point True<br />
|-<br />
| {{mips|MOVZ.fmt}} || Floating Point Move Conditional on Zero<br />
|-<br />
| {{mips|MTC1}} || Move Word to Floating Point<br />
|-<br />
| {{mips|MTHC1}} || Move Word to High Half of Floating Point Register<br />
|}<br />
<br />
== Coprocessor instructions ==<br />
<br />
=== Branch instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|BC2F}} || Branch on COP2 False<br />
|-<br />
| {{mips|BC2T}} || Branch on COP2 True<br />
|-<br />
| <strike>{{mips|BC2FL}}</strike> || Branch on COP2 False Likely<br />
|-<br />
| <strike>{{mips|BC2TL}}</strike> || Branch on COP2 True Likely<br />
|}<br />
<br />
<br />
=== Execute instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|COP2}} || Coprocessor Operation to Coprocessor 2<br />
|}<br />
<br />
=== Memory control instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|DC2}} || Load Doubleword to Coprocessor 2<br />
|-<br />
| {{mips|LWC2}} || Load Word to Coprocessor 2<br />
|-<br />
| {{mips|SDC2}} || Store Doubleword from Coprocessor 2<br />
|-<br />
| {{mips|SWC2}} || Store Word from Coprocessor 2<br />
|}<br />
<br />
<br />
=== Move instructions ===<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CFC2}} || Move Control Word from Coprocessor 2<br />
|-<br />
| {{mips|CTC2}} || Move Control Word to Coprocessor 2<br />
|-<br />
| {{mips|MFC2}} || Move Word from Coprocessor 2<br />
|-<br />
| {{mips|MFHC2}} || Move Word from High Half of Coprocessor 2 Register<br />
|-<br />
| {{mips|MTC2}} || Move Word to Coprocessor 2<br />
|-<br />
| {{mips|MTHC2}} || Move Word to High Half of Coprocessor 2 Register<br />
|}<br />
<br />
<br />
== Privileged instructions ==<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|CACHE}} || Perform Cache Operation<br />
|-<br />
| {{mips|CACHEE}} || Perform Cache Operation EVA<br />
|-<br />
| {{mips|DI}} || Disable Interrupts<br />
|-<br />
| {{mips|EI}} || Enable Interrupts<br />
|-<br />
| {{mips|ERET}} || Exception Return<br />
|-<br />
| {{mips|MFC0}} || Move from {{mips|Coprocessor 0}}<br />
|-<br />
| {{mips|MTC0}} || Move to {{mips|Coprocessor 0}}<br />
|-<br />
| {{mips|RDPGPR}} || Read GPR from Previous Shadow Set<br />
|-<br />
| {{mips|TLBP}} || Probe TLB for Matching Entry<br />
|-<br />
| {{mips|TLBR}} || Read Indexed TLB Entry<br />
|-<br />
| {{mips|TLBWI}} || Write Indexed TLB Entry<br />
|-<br />
| {{mips|TLBWR}} || Write Random TLB Entry<br />
|-<br />
| {{mips|WAIT}} || Enter Standby Mode<br />
|-<br />
| {{mips|WRPGPR}} || Write GPR to Previous Shadow Set<br />
|}<br />
<br />
== EJTAG instructions ==<br />
{| class="wikitable sortable"<br />
! Mnemonic || Description<br />
|-<br />
| {{mips|DERET}} ||Debug Exception Return<br />
|-<br />
| {{mips|SDBBP}} || Software Debug Breakpoint<br />
|}<br />
<br />
== References ==<br />
{{reflist|30em}}<br />
<br />
[[Category:Assembly language]]<br />
[[Category:MIPS]]<br />
[[Category:MIPS32]]<br />
[[Category:RISC instruction set]]<br />
[[Category:Instruction set architecture]]</div>
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