https://en.wikichip.org/w/api.php?action=feedcontributions&user=64.121.146.209&feedformat=atomWikiChip - User contributions [en]2024-03-29T06:27:20ZUser contributionsMediaWiki 1.28.1https://en.wikichip.org/w/index.php?title=Template:amd_zen_3_core_see_also&diff=74846Template:amd zen 3 core see also2018-03-08T22:01:23Z<p>64.121.146.209: </p>
<hr />
<div>{|<br />
|<br />
* {{amd|Zen 3|l=arch}}<br />
** {{amd|Milan|l=core}}<br />
** {{amd|Vermeer|l=core}}<br />
** {{amd|Renoir|l=core}}<br />
** {{amd|Dali|l=core}}<br />
|<br />
{{arrow|up|25px}}Power/Performance<br />
|}</div>64.121.146.209https://en.wikichip.org/w/index.php?title=intel/frequency_behavior&diff=74005intel/frequency behavior2018-02-08T00:06:13Z<p>64.121.146.209: /* Historical behavior */</p>
<hr />
<div>{{intel title|Frequency Behavior}}<br />
The '''Frequency Behavior of Intel's CPUs''' is complex and is governed by multiple mechanisms that perform [[dynamic frequency scaling]] based on the available headroom.<br />
<br />
== Overview ==<br />
With the {{intel|process|increasing transistor budget}} new features are added and the overall core grows in capabilities. Unfortunately, the power constraints have remained the same and in many situations have gotten more restrictive. The result is that despite the [[moore's law|exponentially increasing density]], the [[dark silicon]]'s area is growing just as fast. <br />
<br />
Intel has implemented a number of mechanisms into their architectures to extract additional performance through higher frequency whenever the power and thermal budgets allow.<br />
<br />
* {{intel|Intelligent Power Capability}}<br />
* {{intel|Enhanced Intel SpeedStep Technology}} (EIST) - Introduced with {{intel|Pentium M|l=arch}}, 2005<br />
* {{intel|Dynamic Acceleration Technology}} (DAT) - Introduced with {{intel|Modified Pentium M|l=arch}}/{{intel|Core|l=arch}} 2006<br />
* {{intel|Turbo Boost Technology}} (TBT) - Introduced with {{intel|Nehalem|l=arch}} in 2008<br />
** Turbo Boost Technology 2.0 (TBT 2.0) - Introduced with {{intel|Sandy Bridge|l=arch}} in 2010<br />
* {{intel|Speed Shift Technology}} (SST) - Introduced with {{intel|Skylake|l=arch}} in 2015<br />
* {{intel|Turbo Boost Max Technology}} 3.0 (TBMT) - Introduced with {{intel|Broadwell E|l=core}} in 2016<br />
<br />
== Base, LFM, HFM ==<br />
{| class="wikitable" style="float: left; margin: 10px;"<br />
|-<br />
! colspan="2" | Example [[P-State]] Table<br />
|-<br />
! Voltage !! Frequency<br />
|-<br />
| 1.21 V || 2.8 GHz (HFM)<br />
|-<br />
| 1.18 V || 2.4 GHz<br />
|-<br />
| 1.05 V || 2.0 GHz<br />
|-<br />
| 0.96 V || 1.6 GHz<br />
|-<br />
| 0.93 V || 1.3 GHz<br />
|-<br />
| 0.86 V || 900 MHz<br />
|-<br />
| 0.80 V || 600 MHz (LFM)<br />
|}<br />
With {{intel|EIST}}, which is found on pretty much every Intel's processor since the mid-2000, each processor comes with a series of frequencies and associated voltages (note that a tuple containing the voltage and frequency is called a [[P-State]]). An example frequency table is shown on the left. This table is stored within the read-only processor {{x86|model specific register}} (MSR) and is used to ensure that frequencies do not exceed the lower or upper bound. The lower bound is called the '''Low Frequency Mode''' ('''LFM''') and is the lowest frequency-voltage operating point for a given processor. The upper bound is called the '''High Frequency mode''' ('''HFM''') and is the highest frequency-voltage operating point. Note that the HFM frequency is usually referred to by its advertised name: '''Base Frequency'''.<br />
<br />
Most of the time, the processor does very little work. In order to save power, the processor will drop into a lower [[P-State]] when not under any demanding workloads. The processor will switch around between the various P-States as needed and as dictated by the [[operating system]].<br />
<br />
{{clear}}<br />
<br />
== Base, Non-AVX Turbo, and AVX Turbo ==<br />
[[File:mixed avx-normal workloads with avx512.png|right|400px]]<br />
Because different workloads exhibit different [[die]] thermos and electrical characteristics, they also have different frequencies. Intel organizes workloads into three categories:<br />
<br />
* '''Non-AVX''' - workloads such as SSE and simple (e.g., add/bit) integer vector operations and all other regular instructions.<br />
* '''AVX2 Heavy''' - workloads that make heavy use of complex {{x86|AVX2}} operations (e.g. [[floating point]] and [[integer]] vector multiplications). This also includes the various {{x86|AVX-512}} bit scanning, and other simple (i.e., non INT/FP MUL) operations.<br />
* '''AVX-512 Heavy''' - workloads that make use of complex {{x86|AVX-512}} operations, including operations such as floating point and integer vector multiplications.<br />
<br />
The frequency of each core is determined independently based on the workload described above. That is, cores running Non-AVX workloads can enjoy the full regular turbo frequency, whereas cores executing {{x86|AVX-512}} or {{x86|AVX2}} will operate at their own designated turbo frequencies.<br />
<br />
Due to all of that, each processor has the following properties:<br />
<br />
{| class="wikitable"<br />
|-<br />
! Mode !! Example Workload !! Absolute Guaranteed<br>Lowest Frequency !! Absolute<br>Highest Frequency<br />
|-<br />
| Non-AVX || SSE, light AVX2 Integer Vector (non-MUL), All regular instruction || Base Frequency || Turbo Frequency<br />
|-<br />
| {{x86|AVX2}} Heavy || All AVX2 operations, light AVX-512 (non-FP, Int Vect non-MUL) || AVX2 Base || AVX2 Turbo<br />
|-<br />
| {{x86|AVX-512}} Heavy || All heavy AVX-512 operations || AVX-512 Base || AVX-512 Turbo<br />
|}<br />
<br />
=== Historical behavior ===<br />
In {{intel|Haswell|l=arch}}, an {{x86|AVX2}} workload on one core meant all cores were capped at ''AVX2 Turbo'' frequency. This had the undesirable effect of reducing performance for non-AVX workloads on cores that were unrelated to the cores executing AVX2 workloads. This behavior was changed with {{intel|Broadwell|l=arch}} which grouped cores executing AVX2 workloads together and cores executing non-AVX workloads separately, allowing the former cores group to execute at the lower AVX2 turbo frequency while having the later cores group execute at full non-AVX2 turbo.<br />
<br />
::[[File:broadwell avx turbo changes.png|700px]]<br />
<br />
== See also ==<br />
* AMD's {{amd|Frequency Behavior}}<br />
<br />
[[Category:power management mechanisms by intel]]</div>64.121.146.209https://en.wikichip.org/w/index.php?title=10_nm_lithography_process&diff=6605710 nm lithography process2017-10-20T04:51:57Z<p>64.121.146.209: /* Intel */ typo</p>
<hr />
<div>{{lithography processes}}<br />
The '''10 nanometer (10 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[14 nm process]]. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 10 nm node is currently being introduced and is set to get replaced by the [[7 nm process]] in 2019.<br />
<br />
== Industry ==<br />
At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]].<br />
<br />
Due to marketing names, geometries vary greatly between leading manufactures. Although both TSMC and Samsung's 10nm processes are slightly denser than Intel's 14nm in raw logic density, they are far closer to Intel's 14nm than they are to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm).<br />
<br />
{{10 nm comp<br />
<!-- Intel --><br />
| process 1 fab = [[Intel]]<br />
| process 1 name = P1274 (CPU) / P1275 (SoC)<br />
| process 1 date = 2017<br />
| process 1 lith = 193 nm<br />
| process 1 immersion = Yes<br />
| process 1 exposure = [[Self-Aligned Quad Patterning|SAQP]]<br />
| process 1 wafer type = Bulk<br />
| process 1 wafer size = 300 mm<br />
| process 1 transistor = FinFET<br />
| process 1 volt = 0.70 V<br />
| process 1 delta from = [[14 nm]] Δ<br />
| process 1 fin pitch = 34 nm<br />
| process 1 fin pitch Δ = 0.81x<br />
| process 1 fin width = 7 nm<br />
| process 1 fin width Δ = 0.88x<br />
| process 1 fin height = 53 nm<br />
| process 1 fin height Δ = 1.26x<br />
| process 1 gate len = &nbsp;<br />
| process 1 gate len Δ = &nbsp;<br />
| process 1 cpp = 54 nm<br />
| process 1 cpp Δ = 0.77x<br />
| process 1 mmp = 36 nm<br />
| process 1 mmp Δ = 0.69x<br />
| process 1 sram hp = 0.0441 µm²<br />
| process 1 sram hp Δ = 0.62x<br />
| process 1 sram hd = 0.0312 µm²<br />
| process 1 sram hd Δ = 0.62x<br />
| process 1 sram lv = 0.0367 µm²<br />
| process 1 sram lv Δ = 0.62x<br />
| process 1 dram = &nbsp;<br />
| process 1 dram Δ = &nbsp;<br />
<br />
<!-- TSMC --><br />
| process 2 fab = [[TSMC]]<br />
| process 2 name = 10FF<br />
| process 2 date = June 2017<br />
| process 2 lith = 193 nm<br />
| process 2 immersion = Yes<br />
| process 2 exposure = SAQP<br />
| process 2 wafer type = Bulk<br />
| process 2 wafer size = 300 mm<br />
| process 2 transistor = FinFET<br />
| process 2 volt = 0.70 V<br />
| process 2 delta from = [[16 nm]] Δ<br />
| process 2 fin pitch = &nbsp;<br />
| process 2 fin pitch Δ = &nbsp;<br />
| process 2 fin width = &nbsp;<br />
| process 2 fin width Δ = &nbsp;<br />
| process 2 fin height = &nbsp;<br />
| process 2 fin height Δ = &nbsp;<br />
| process 2 gate len = &nbsp;<br />
| process 2 gate len Δ = &nbsp;<br />
| process 2 cpp = 66 nm <sub>(64 nm<sup>*</sup>)</sub><br />
| process 2 cpp Δ = 0.73x<br />
| process 2 mmp = 44 nm <sub>(42 nm<sup>*</sup>)</sub><br />
| process 2 mmp Δ = 0.69x<br />
| process 2 sram hp = &nbsp;<br />
| process 2 sram hp Δ = &nbsp;<br />
| process 2 sram hd = 0.042 µm²<br />
| process 2 sram hd Δ = 0.57x<br />
| process 2 sram lv = &nbsp;<br />
| process 2 sram lv Δ = &nbsp;<br />
| process 2 dram = &nbsp;<br />
| process 2 dram Δ = &nbsp;<br />
<br />
<!-- Samsung --><br />
| process 3 fab = [[Samsung]]<br />
| process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power Performance</info>, 10LPU<info>3<sup>rd</sup> generation; 10 nm Low Power Ultimate</info><br />
| process 3 date = April 2017<br />
| process 3 lith = 193 nm<br />
| process 3 immersion = Yes<br />
| process 3 exposure = [[LELELE]]<br />
| process 3 wafer type = Bulk<br />
| process 3 wafer size = 300 mm<br />
| process 3 transistor = FinFET<br />
| process 3 volt = 0.75 V<br />
| process 3 delta from = [[14 nm]] Δ<br />
| process 3 fin pitch = &nbsp;<br />
| process 3 fin pitch Δ = &nbsp;<br />
| process 3 fin width = &nbsp;<br />
| process 3 fin width Δ = &nbsp;<br />
| process 3 fin height = &nbsp;<br />
| process 3 fin height Δ = &nbsp;<br />
| process 3 gate len = &nbsp;<br />
| process 3 gate len Δ = &nbsp;<br />
| process 3 cpp = 68 nm<br />
| process 3 cpp Δ = 0.87x<br />
| process 3 mmp = 51 nm<br />
| process 3 mmp Δ = 0.80x<br />
| process 3 sram hp = 0.049 µm²<br />
| process 3 sram hp Δ = 0.61x<br />
| process 3 sram hd = 0.040 µm²<br />
| process 3 sram hd Δ = 0.63x<br />
| process 3 sram lv = &nbsp;<br />
| process 3 sram lv Δ = &nbsp;<br />
| process 3 dram = &nbsp;<br />
| process 3 dram Δ = &nbsp;<br />
<br />
<!-- Common Platform --><br />
<br />
| process 4 fab = [[Common Platform Alliance]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[STMicroelectronics]], [[UMC]]</info> Paper<br />
| process 4 name = &nbsp;<br />
| process 4 date = &nbsp;<br />
| process 4 lith = 193 nm<br />
| process 4 immersion = Yes<br />
| process 4 exposure = SADP<br />
| process 4 wafer type = Bulk/SOI<br />
| process 4 wafer size = 300 mm<br />
| process 4 transistor = FinFET<br />
| process 4 volt = 0.75 V<br />
| process 4 delta from = [[14 nm]] Δ<br />
| process 4 fin pitch = &nbsp;<br />
| process 4 fin pitch Δ = &nbsp;<br />
| process 4 fin width = &nbsp;<br />
| process 4 fin width Δ = &nbsp;<br />
| process 4 fin height = &nbsp;<br />
| process 4 fin height Δ = &nbsp;<br />
| process 4 gate len = 20 nm<br />
| process 4 gate len Δ = 1.00x;<br />
| process 4 cpp = 64 nm<br />
| process 4 cpp Δ = 0.80x<br />
| process 4 mmp = 48 nm<br />
| process 4 mmp Δ = 0.75x<br />
| process 4 sram hp = &nbsp;<br />
| process 4 sram hp Δ = &nbsp;<br />
| process 4 sram hd = 0.053 µm²<br />
| process 4 sram hd Δ = 0.65x<br />
| process 4 sram lv = &nbsp;<br />
| process 4 sram lv Δ = &nbsp;<br />
| process 4 dram = &nbsp;<br />
| process 4 dram Δ = &nbsp;<br />
}}<br />
<br />
'''<sup>*</sup>''' - Value reported from IEEE ISSCC/IEDM/VLSI Conference.<br />
<br />
=== Intel ===<br />
{{see also|intel/process|l1=Intel's Process Technology History}}<br />
[[File:intel 10nm fin.png|right|200px]]<br />
Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is Intel's first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) with production starting in the second half of 2017. Intel detailed {{intel|Hyper-Scaling}}, a marketing term for a suite of techniques used to [[transistor scaling|scale a transistor]], SAQP, a single dummy gate and [[contact over active gate]] (COAG). Intel's initial 10 nm process has up to 60% lower power and 25% better performance than their initial 14 nm but will actually have lower performance than their "14nm++" process. Intel expect their "10nm+" process to surpass that.<br />
<br />
Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node.<br />
At 10nm the wires become so small that the barrier layer takes up most of the interconnect, resulting in less space for the copper itself. As the cross section of the wire gets smaller the resistance rises exponentially. Cobalt aims to address this issue, it does not diffuse in the surrounding material, so the barrier layer can be reduced. And even though it has a higher resistance than copper in bulk, it has a two times lower resistance in very small wires. This can be attributed to the larger wires because of the reduced barrier layer and the larger grain size, witch reduces the electron scattering. It also has 10x better resistance to electron-migration. <br />
<br />
Intel will leverage their initial 10nm process for their {{intel|Cannonlake|l=arch}}-based microprocessors which are used exclusively for mobile. They will then utilize their second generation, "10nm+" process, for {{intel|Icelake|l=arch}}-based processors which will be used for the mainstream and server platform.<br />
<br />
{{clear}}<br />
<br />
=== Samsung ===<br />
[[File:ss 14-10nm.png|right|500px]]<br />
Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 mm contacted gate pitch, 51 nm metal pitch, dual-depth [[shallow trench isolation]] (STI), and had single dummy gate.<br />
<br />
{| class="collapsible collapsed wikitable"<br />
|-<br />
! colspan="2" | Samsung 128 Mib SRAM demo 10 nm wafer<br />
|-<br />
|<br />
<table class="wikitable"><br />
<tr><th>Technology</th><td>10nm FinFET</td></tr><br />
<tr><th>Supply voltage</th><td>1.8 V (i/o)</td></tr><br />
<tr><th>Bit cell size</th><td>0.040 µm²</td></tr><br />
<tr><th>macro configs</th><td>256x512 Kib</td></tr><br />
<tr><th>Capacity</th><td>128 Mib</td></tr><br />
<tr><th>Test Features</th><td>Programmable E-fuse</td></tr><br />
<tr><th>Die Size</th><td>75.6mm²</td></tr><br />
</table><br />
| [[File:samsung 10nm SRAM block.png|400px]]<br />
|}<br />
<br />
Samsung's initial process was 10LPE (10 Low-Power Early) which was replaced by second generation evolved process 10LPP (10 Low-Power Plus). Samsung intends to introduce a third generational enhanced 10nm process called 8LPP (8 Low Power Plus) which will further improve performance and introduce a small density increase through design rules and cell enhancements. 8LPP improvements over 10LPP is similar to their 11LPP improvements over their 14LPP. It's worth noting that Samsung intends 8LPP to be their last non-[[EVU]] node. All subsequent nodes will use EUV.<br />
<br />
=== TSMC ===<br />
TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. TSMC claims the 10FF process will have 15% higher performance while consuming 35% less power.<br />
{{clear}}<br />
[[File:10nm tsmc.jpeg|200px]]<br />
<br />
== 10 nm Microprocessors==<br />
* Apple<br />
** {{apple|A10X}}<br />
** {{apple|A11 Bionic}}<br />
* HiSilicon<br />
** {{hisil|Kirin}}<br />
* MediaTek <br />
** {{mediatek|Helio}}<br />
* Qualcomm <br />
** {{qualcomm|Snapdragon 800}}<br />
** {{qualcomm|Centriq}}<br />
* Xiaomi<br />
** {{xiaomi|Surge}}<br />
{{expand list}}<br />
<br />
== 10 nm Microarchitectures==<br />
* Intel<br />
** {{intel|Cannonlake|l=arch}}<br />
** {{intel|Icelake|l=arch}}<br />
** {{intel|Tigerlake|l=arch}}<br />
** {{intel|Sapphire Rapids|l=arch}}<br />
* Qualcomm<br />
** {{qualcomm|Falkor|l=arch}}<br />
{{expand list}}<br />
<br />
== Documents ==<br />
* [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]]<br />
* [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm]]<br />
* [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law]]<br />
<br />
== References ==<br />
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.<br />
* Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.<br />
* Seo, K-I., et al. "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.<br />
* Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.<br />
* Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).<br />
* Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.<br />
* Samsung's actual transitor size was measured by ChipWorks/TechInsight based on the [[Qualcomm]] {{qualcomm|Snapdragon 835}} which is manufactured on Samsung's 10nm process. <br />
* [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis]<br />
<br />
[[Category:Lithography]]</div>64.121.146.209https://en.wikichip.org/w/index.php?title=amd/ryzen_7/1700&diff=64481amd/ryzen 7/17002017-09-21T03:47:44Z<p>64.121.146.209: </p>
<hr />
<div>{{amd title|Ryzen 7 1700}}<br />
{{mpu<br />
|name=AMD Ryzen 7 1700<br />
|image=ryzen 7 1700.svg<br />
|image size=250px<br />
|designer=AMD<br />
|manufacturer=GlobalFoundries<br />
|model number=1700<br />
|part number=YD1700BBAEBOX<br />
|part number 2=YD1700BBM88AE<br />
|market=Desktop<br />
|first announced=February 22, 2017<br />
|first launched=March 2, 2017<br />
|release price=$329<br />
|family=Ryzen 7<br />
|series=Ryzen<br />
|locked=No<br />
|frequency=3,000 MHz<br />
|turbo frequency1=3,700 MHz<br />
|turbo frequency2=3,700 MHz<br />
|turbo frequency3=3,100 MHz<br />
|turbo frequency4=3,100 MHz<br />
|turbo frequency5=3,100 MHz<br />
|turbo frequency6=3,100 MHz<br />
|turbo frequency7=3,100 MHz<br />
|turbo frequency8=3,100 MHz<br />
|bus links=4<br />
|bus rate=8 GT/s<br />
|clock multiplier=30<br />
|cpuid=800F11<br />
|isa=x86-64<br />
|isa family=x86<br />
|microarch=Zen<br />
|chipset=Promontory<br />
|core name=Summit Ridge<br />
|core family=23<br />
|core model=1<br />
|core stepping=1<br />
|process=14 nm<br />
|transistors=4,800,000,000<br />
|technology=CMOS<br />
|die area=213 mm²<br />
|word size=64 bit<br />
|core count=8<br />
|thread count=16<br />
|max cpus=1<br />
|max memory=64 GiB<br />
|tdp=65 W<br />
|package module 1={{packages/amd/socket am4}}<br />
|turbo frequency=Yes<br />
}}<br />
'''Ryzen 7 1700''' is a {{arch|64}} [[octa-core]] high-end performance [[x86]] desktop microprocessor introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1700 operates at a base frequency of 3 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of up to 3.7 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.<br />
<br />
== Cache ==<br />
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}<br />
{{cache size<br />
|l1 cache=768 KiB<br />
|l1i cache=512 KiB<br />
|l1i break=8x64 KiB<br />
|l1i desc=4-way set associative<br />
|l1d cache=256 KiB<br />
|l1d break=8x32 KiB<br />
|l1d desc=8-way set associative<br />
|l1d policy=write-back<br />
|l2 cache=4 MiB<br />
|l2 break=8x512 KiB<br />
|l2 desc=8-way set associative<br />
|l2 policy=write-back<br />
|l3 cache=16 MiB<br />
|l3 break=2x8 MiB<br />
|l3 desc=16-way set associative<br />
}}<br />
<br />
== Memory controller ==<br />
This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).<br />
{{memory controller<br />
|type=DDR4-2666<br />
|ecc=Yes<br />
|max mem=64 GiB<br />
|controllers=2<br />
|channels=2<br />
|max bandwidth=39.74 GiB/s<br />
|bandwidth schan=19.87 GiB/s<br />
|bandwidth dchan=39.74 GiB/s<br />
}}<br />
<br />
{{amd ryzen memory configs}}<br />
<br />
== Expansions ==<br />
The Ryzen 7 1700 includes 20 PCIe lanes supporting Gen1, Gen2, and Gen3: 16 for a [[DGP]] and 4 for storage (NVMe or 2 ports SATA Express). PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16). <br />
{{expansions<br />
| pcie revision = 3.0<br />
| pcie lanes = 20<br />
| pcie config = 1x16+1x4<br />
| sata revision = 3.0<br />
| sata ports = 4<br />
| usb revision = 3.0<br />
| usb revision 2 = 2.0<br />
| usb ports = 4<br />
| usb rate = 5 Gbit/s<br />
| uart = Yes<br />
| uart ports = 4<br />
| gp io = 6 ports<br />
}}<br />
* eMMC, LPC, SMBus, SPI/eSPI<br />
<br />
== Audio ==<br />
Support Azalia High Definition Audio<br />
<br />
== Graphics ==<br />
This processor has no integrated graphics.<br />
<br />
== Features == <br />
{{x86 features<br />
|real=Yes<br />
|protected=Yes<br />
|smm=Yes<br />
|fpu=Yes<br />
|x8616=Yes<br />
|x8632=Yes<br />
|x8664=Yes<br />
|nx=Yes<br />
|mmx=Yes<br />
|emmx=Yes<br />
|sse=Yes<br />
|sse2=Yes<br />
|sse3=Yes<br />
|ssse3=Yes<br />
|sse41=Yes<br />
|sse42=Yes<br />
|sse4a=Yes<br />
|avx=Yes<br />
|avx2=Yes<br />
<br />
|abm=Yes<br />
|tbm=No<br />
|bmi1=Yes<br />
|bmi2=Yes<br />
|fma3=Yes<br />
|fma4=No<br />
|aes=Yes<br />
|rdrand=Yes<br />
|sha=Yes<br />
|xop=No<br />
|adx=Yes<br />
|clmul=Yes<br />
|f16c=Yes<br />
|tbt1=No<br />
|tbt2=No<br />
|tbmt3=No<br />
|bpt=No<br />
|eist=No<br />
|sst=No<br />
|flex=No<br />
|fastmem=No<br />
|isrt=No<br />
|sba=No<br />
|mwt=No<br />
|sipp=No<br />
|att=No<br />
|ipt=No<br />
|tsx=No<br />
|txt=No<br />
|ht=No<br />
|vpro=No<br />
|vtx=No<br />
|vtd=No<br />
|ept=No<br />
|mpx=No<br />
|sgx=No<br />
|securekey=No<br />
|osguard=No<br />
|3dnow=No<br />
|e3dnow=No<br />
|smartmp=No<br />
|powernow=No<br />
|amdvi=Yes<br />
|amdv=Yes<br />
|rvi=No<br />
|smt=Yes<br />
|sensemi=Yes<br />
|xfr=No<br />
}}<br />
<br />
* This model has partial {{amd|XFR}} support, allowing for an additional +[[amd xfr headroom::50 MHz]] boost frequency.<br />
<br />
== Die Shot ==<br />
{{see also|amd/microarchitectures/zen#Die|l1=Zen § Die Shot}}<br />
* [[14 nm process]]<br />
* 12 metal layers<br />
* 2,000 meters of signals<br />
* 4,800,000,000 transistors<br />
* 213 mm² die size<br />
<br />
[[File:amd zen octa-core die shot.png|950px]]</div>64.121.146.209https://en.wikichip.org/w/index.php?title=intel/microarchitectures/skylake_(client&diff=64471intel/microarchitectures/skylake (client2017-09-21T03:32:16Z<p>64.121.146.209: Redirected page to intel/microarchitectures/skylake (client)</p>
<hr />
<div>#REDIRECT [[intel/microarchitectures/skylake (client)]]</div>64.121.146.209https://en.wikichip.org/w/index.php?title=WikiChip:wanted_chips&diff=64132WikiChip:wanted chips2017-09-16T13:53:34Z<p>64.121.146.209: </p>
<hr />
<div>'''The following wanted/requested chips should be documented.''' Stopping by to list a missing chip? Fantastic! just add its name to the list! If it's a really obscure chip, a link to a source wouldn't hurt!<br />
<br />
<br />
<br />
= Missing/Requested/Wanted chips list =<br />
* Tilera / Mellanox<br />
* MIT Raw http://groups.csail.mit.edu/cag/raw/<br />
* [[Transmeta]] / [[Crusoe]] / [[Efficeon]]<br />
* pretty much everything listed here http://ps-2.kev009.com/powerpc-faq/<br />
* [[Quantum Effect Device]]/[[Quantum Effect Designs]] / [[PowerPC 603q]] / etc..<br />
* Stretch S5000<br />
* [[Kalray]] / [[MPPA-256]] / [[MPPA2-256]]<br />
* [[Sunway TaihuLight]]<br />
** [[ShenWei]] / [[SW26010]] / [[SW1600]] / [[SW-1]]/[[SW-2]]/[[SW-3]]<br />
* Godson-1 September 28, 2002 Godson-2/Godson-3 - Institute of Computing Technology, Chinese Academy of Sciences<br />
* Intersil ISD-8, was announced in 1994 (can see it [http://chiclassiccomp.org/docs/content/publications/ACS_Newsletter/ACS_Newsletter_3_7.pdf here], and [https://books.google.com/books?id=XeazBgAAQBAJ&lpg=PA72&ots=eR_z2Or3Cf&dq=fairchild%20PPS-25&pg=PA72#v=onepage&q&f=false here]) unknown if ever released or was codename possibly or the Intersil 6100<br />
* Mostek MK5065<br />
* TCL41, 43, 45 <br />
* [[Intel Pentium A1020]]<br />
* [http://apt.cs.manchester.ac.uk/projects/SpiNNaker/hardware/ SpiNNaker]<br />
* Crypto CoPros<br />
** IBM 4758<br />
** IBM 4578<br />
** IBM 4765<br />
** IBM 4764<br />
** IBM 4764-001 [https://www-03.ibm.com/security/cryptocards/pciecc/pdf/PCIe_Spec_Sheet.pdf src]<br />
* [[Intel 8031]]<br />
* [[Intel 8035]]<br />
* [[Intel 8039]]<br />
* [[Intel 8048]]<br />
* [[Intel 8051]]<br />
* [[Intel 8086]]<br />
* [[Intel 8087]]<br />
* [[Intel 8088]]<br />
* [[Intel 8748]]<br />
* [[Intel 8751]]<br />
* [[Intel 80186]]<br />
* [[Intel 80188]]<br />
* [[Intel 80286]]<br />
* [[Intel 80376]]<br />
* [[Intel 80486]]<br />
* [[Intel 80486 overdrive]]<br />
* [[Intel 80860]]<br />
* [[Intel n80960]]<br />
* [[Intel Pentium II]]<br />
* [[Intel Pentium MMX]]<br />
* [[Intel Pentium III]]<br />
(list not complete)<br />
<br />
4-bit ones<br />
* [[TLCS-47]]<br />
<br />
Some 8-bit ones<br />
* [[Intel 8080]]<br />
* [[Intel 8085]]<br />
* [[Burroughs Mini-D]]<br />
* [[Mostek 5065]]<br />
* [[MOS Technology 6502]]<br />
* [[Motorola 6800]]<br />
* [[Motorola 6809]]<br />
* [[Motorola 6801]]<br />
* [[Motorola 6803]]<br />
* [[National SC/MP]]<br />
* [[Signetics 2650]]<br />
* [[Rockwell PPS-8]]<br />
* [[RCA COSMAC 1802]]<br />
* [[RCA COSMAC 1802]]<br />
* [[Zilog Z8]]<br />
* [[Zilog Z80]]<br />
* [[Zilog eZ80]]<br />
* [[Zilog Z180]]<br />
* [[Signetics 8X300]]<br />
* [[Freescale HC08]]<br />
* [[Freescale HC11]]<br />
* [[Hudson Soft HuC6280]]<br />
* [[microchip/PIC10]]<br />
* [[microchip/PIC12]]<br />
* [[microchip/PIC16]]<br />
* [[Ricoh 2A03]]<br />
* [[Ricoh 2A07]]<br />
* [[TLCS-870]]<br />
* [[National COP8]]<br />
* [[AMI 7200]]<br />
* [[Intel Core i7-7700HQ]] (Kaby Lake-H, quad-core 2.8 GHz, 45W)<br />
* [[atmel/atmega]], in particular the Atmel ATmega328 used in most Arduino boards<br />
* [[cypress/PSoC 1]]<br />
* [[cypress/PSoC 4]]<br />
* [[cypress/PSoC 5]]<br />
* [[parallax/Basic Stamp]]<br />
[[File:Basic stamp 2p24.jpg|thumb|right|200px|[[Parallax]]'s Basic Stamp 2 board ({{parallax|BS2P24}}). This board has a [[CPU]] and a [[BASIC]] [[interpreter]] on-board. (from [[program]]).]]<br />
* [[parallax/Propeller]]<br />
* [[Nios II]] softcore CPU for FPGA<br />
* [[MicroBlaze]] softcore CPU for FPGA<br />
* [[DLX]] by John L. Hennessy and David A. Patterson<br />
* [[Elbrus]]<br />
* GreenArrays (asynchronous) F18A/F18B GA4/GA32/GA40/GA144<br />
* [[Sun]] {{sun|Rock}}<br />
* [[NovaThor]]<br />
* [[MediaTek MT6735]]<br />
* [[Microsoft Xenon]]</div>64.121.146.209