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User contributions
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https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_3&diff=99277
amd/microarchitectures/zen 3
2021-09-11T13:07:31Z
<p>37.201.198.111: Undo revision 99116 by 31.42.10.254 (talk) Increased was correct</p>
<hr />
<div>{{amd title|Zen 3|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Zen 3<br />
|designer=AMD<br />
|manufacturer=TSMC<br />
|manufacturer 2=GlobalFoundries<br />
|introduction=October 8, 2020<br />
|process=7nm<br />
|cores=64<br />
|cores 2=56<br />
|cores 3=48<br />
|cores 4=32<br />
|cores 5=28<br />
|cores 6=24<br />
|cores 7=16<br />
|cores 8=12<br />
|cores 9=8<br />
|cores 10=6<br />
|type=Superscalar<br />
|oooe=Yes<br />
|speculative=Yes<br />
|renaming=Yes<br />
|stages=19<br />
|decode=4-way<br />
|isa=x86-64<br />
|extension=MOVBE<br />
|extension 2=MMX<br />
|extension 3=SSE<br />
|extension 4=SSE2<br />
|extension 5=SSE3<br />
|extension 6=SSSE3<br />
|extension 7=SSE4A<br />
|extension 8=SSE4.1<br />
|extension 9=SSE4.2<br />
|extension 10=POPCNT<br />
|extension 11=AVX<br />
|extension 12=AVX2<br />
|extension 13=AES<br />
|extension 14=PCLMUL<br />
|extension 15=FSGSBASE<br />
|extension 16=RDRND<br />
|extension 17=FMA3<br />
|extension 18=F16C<br />
|extension 19=BMI<br />
|extension 20=BMI2<br />
|extension 21=RDSEED<br />
|extension 22=ADCX<br />
|extension 23=PREFETCHW<br />
|extension 24=CLFLUSHOPT<br />
|extension 25=XSAVE<br />
|extension 26=SHA<br />
|extension 27=UMIP<br />
|extension 28=CLZERO<br />
|predecessor=Zen 2<br />
|predecessor link=amd/microarchitectures/zen 2<br />
|successor=Zen 4<br />
|successor link=amd/microarchitectures/zen 4<br />
}}<br />
'''Zen 3''' is a [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|Zen 2}}. It was publicly released on October 8, 2020. Mainstream Desktop processors hit shelves on November 5, 2020.<br />
<br />
== History ==<br />
[[File:amd zen future roadmap.jpg|400px|right]]<br />
Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]].<br />
<br />
== Products ==<br />
[[File:amd zen2-3 roadmap.png|400px|right]]<br />
{{future information}}<br />
<br />
{| class="wikitable"<br />
|-<br />
! Product Line !! Cores/Threads !! Target<br />
|-<br />
| EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]]<br />
|-<br />
| {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing<br />
|-<br />
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors<br />
|-<br />
| Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors<br />
|-<br />
| Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with GPU<br />
|}<br />
<br />
== Process technology ==<br />
Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]], the same process used in Zen 2 Refresh processors.<br />
<br />
== Architecture ==<br />
<br />
There is very limited information available about the architectural improvements of Zen 3.<br />
<br />
=== Key changes from {{\\|Zen 2}} ===<br />
* CCD<br />
** Unified 8-core CCX (from 2x 4-Core CCX per CCD) <br />
** 32 MiB L3$ available equally to all cores in CCD.<br />
*** Increased L3 latency (~46 cycles, up from ~40 cycles)<br />
* Core<br />
** Higher [[IPC]] (AMD self-reported +19% IPC)<br />
** Front-end<br />
** Increased branch prediction bandwidth<br />
*** "zero-bubble" branch prediction<br />
*** L1 BTB doubled from 512 to 1024 entries<br />
** Improved prefetching<br />
** Improved µop cache<br />
* Back-end<br />
** Floating point unit:<br />
*** FMA latency reduced by 1 cycle from 5 to 4.<br />
*** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.<br />
*** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.<br />
*** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughput.<br />
*** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.<br />
** Integer unit:<br />
*** Integer physical register file increased from 180 to 192 entries<br />
*** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.<br />
*** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.<br />
*** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.<br />
*** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.<br />
** Load/store:<br />
*** Load throughput increased from 2 to 3, if not 256b.<br />
*** Store throughput increased from 1 to 2, if not 256b.<br />
*** Store queue increase from 48 to 64 slots.<br />
*** Page table walkers tripled from 2 to 6 for TLB miss handling.<br />
{{expand list}}<br />
<br />
=== New Instructions ===<br />
Zen 3 introduced the following ISA enhancements:<br />
<br />
* {{x86|VAES}} - 256-bit Vector AES instructions<br />
** <code>VAESDEC</code> - AES Decryption Round<br />
** <code>VAESDECLAST</code> - AES Last Decryption Round<br />
** <code>VAESENC</code> - AES Encryption Round<br />
** <code>VAESENCLAST</code> - AES Last Encryption Round<br />
* <code>{{x86|VPCLMULQDQ}}</code> - 256-bit Vector Carry-Less Multiplication of Quadwords<br />
* {{x86|PCID}} - Process Context Identifiers<br />
** <code>{{x86|INVPCID}}</code> - Invalidate TLB entry(s) in a specified PCID<br />
* {{x86|INVLPGB}} - Broadcast TLB flushing<br />
** <code>INVLPGB</code> - Invalidate TLB entry(s) with broadcast to all processors<br />
** <code>TLBSYNC</code> - Synchronize TLB invalidations<br />
* {{x86|PKU}} - Memory Protection Keys for Users<br />
** <code>RDPKRU</code> - Read Protection Key Rights<br />
** <code>WRPKRU</code> - Write Protection Key Rights<br />
* {{x86|CET|CET_SS}} - Control-flow Enforcement Technology / Shadow Stack<br />
** <code>CLRSSBSY</code>, <code>INCSSP</code>, <code>RDSSP</code>, <code>RSTORSSP</code>, <code>SAVEPREVSSP</code>, <code>SETSSBSY</code>, <code>WRSS</code>, <code>WRUSS</code><br />
* {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging<br />
** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code><br />
* {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf">[https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf "Security Analysis of AMD Predictive Store Forwarding"], March 2021</ref><br />
<br />
Sources:<ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref><ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref><ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref><br />
<br />
=== Memory Hierarchy ===<br />
==== Data and Instruction Caches ====<br />
* L0 Op Cache:<br />
** 4,096 Ops per core, 8-way set associative<br />
** 8 Op line size<br />
** Parity protected<br />
* L1I Cache:<br />
** 32 KiB per core, 8-way set associative<br />
** 64 B line size<br />
** Parity protected<br />
* L1D Cache:<br />
** 32 KiB per core, 8-way set associative<br />
** 64 B line size<br />
** Write-back policy<br />
** 4-5 cycles latency for Int<br />
** 7-8 cycles latency for FP<br />
** ECC<br />
* L2 Cache:<br />
** 512 KiB per core, 8-way set associative<br />
** 64 B line size<br />
** Write-back policy<br />
** Inclusive of L1<br />
** ≥ 12 cycles latency<br />
** ECC<br />
* L3 Cache:<br />
** "{{amd|Milan|l=core}}": 32 MiB/CCX, up to 256 MiB total<br />
** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total<br />
** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs<br />
** Shared by all cores in the CCX, configurable<ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref><br />
** 16-way set associative<br />
** 64 B line size<br />
** L2 [[victim cache]]<br />
** Write-back policy<br />
** 46 cycles average load-to-use latency<br />
** ECC<br />
** QoS Monitoring and Enforcement V2.0<br />
<br />
==== Translation Lookaside Buffers ====<br />
* ITLB<br />
** 64 entry L1 TLB, fully associative, all page sizes<br />
** 512 entry L2 TLB, 8-way set associative<br />
*** 4-Kbyte and 2-Mbyte pages<br />
** Parity protected<br />
* DTLB<br />
** 64 entry L1 TLB, fully associative, all page sizes<br />
** 2,048 entry L2 TLB, 16-way set associative<br />
*** 4-Kbyte and 2-Mbyte pages, PDEs to speed up table walks<br />
** Parity protected<br />
<br />
All caches and TLBs are competitively shared in multi-threaded mode.<br />
<br />
==== System DRAM ====<br />
* EPYC 7003 "{{amd|Milan|l=core}}":<br />
** 8 channels per socket, up to 16 DIMMs, max. 4 TiB<br />
** Up to PC4-25600L (DDR4-3200), ECC supported<br />
** SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM, NVDIMM-N<br />
* Ryzen 5000 "{{amd|Vermeer|l=core}}":<br />
** 2 channels, up to 4 DIMMs, max. 128 GiB<br />
** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported<br />
* Ryzen 5000 APU "{{amd|Cezanne|l=core}}":<br />
** DDR4-3200 or LPDDR4-4266<br />
<br />
Sources:<ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref><ref name="amd-55898-ppr-1901">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref><br />
<br />
== All Zen 3 Chips ==<br />
<br />
<!-- NOTE:<br />
This table is generated automatically from the data in the actual articles.<br />
If a microprocessor is missing from the list, an appropriate article for it needs to be<br />
created and tagged accordingly.<br />
<br />
Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips<br />
--><br />
{{comp table start}}<br />
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19"><br />
{{comp table header|main|20:List of all Zen 3-based Processors}}<br />
{{comp table header|main|12:Processor|4:Features}}<br />
{{comp table header|cols|Price|Process|Launched|Family|Core|C|T|TDP|L3|Base|Turbo|Max Mem|SMT|SEV|SME|TSME}}<br />
{{comp table header|lsep|25:[[Uniprocessors]]}}<br />
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::1]]<br />
|?full page name<br />
|?model number<br />
|?release price<br />
|?process<br />
|?first launched<br />
|?microprocessor family<br />
|?core name<br />
|?core count<br />
|?thread count<br />
|?tdp<br />
|?l3$ size<br />
|?base frequency#GHz<br />
|?turbo frequency#GHz<br />
|?max memory#GiB<br />
|?has simultaneous multithreading<br />
|?has amd secure encrypted virtualization technology<br />
|?has amd secure memory encryption technology<br />
|?has amd transparent secure memory encryption technology<br />
|format=template<br />
|template=proc table 3<br />
|userparam=18:15<br />
|mainlabel=-<br />
|valuesep=,<br />
|limit=100<br />
}}<br />
{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}<br />
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::>>1]]<br />
|?full page name<br />
|?model number<br />
|?release price<br />
|?process<br />
|?first launched<br />
|?microprocessor family<br />
|?core name<br />
|?core count<br />
|?thread count<br />
|?tdp<br />
|?l3$ size<br />
|?base frequency#GHz<br />
|?turbo frequency#GHz<br />
|?max memory#GiB<br />
|?has simultaneous multithreading<br />
|?has amd secure encrypted virtualization technology<br />
|?has amd secure memory encryption technology<br />
|?has amd transparent secure memory encryption technology<br />
|format=template<br />
|template=proc table 3<br />
|userparam=18:15<br />
|mainlabel=-<br />
|valuesep=,<br />
|limit=100<br />
}}<br />
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]]}}<br />
</table><br />
{{comp table end}}<br />
<br />
== Designers ==<br />
* Mark Evers, Chief Architect<br />
<br />
== Bibliography ==<br />
* AMD 'Tech Day', February 22, 2017<br />
* AMD 2017 Financial Analyst Day, May 16, 2017<br />
<br />
== References ==<br />
<references/><br />
<br />
== See Also ==<br />
* AMD {{\\|Zen}}, {{\\|Zen 2}}<br />
* Intel {{intel|Tigerlake|l=arch}}<br />
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]<br />
* Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews]</div>
37.201.198.111
https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_3&diff=98445
amd/microarchitectures/zen 3
2021-01-24T20:23:14Z
<p>37.201.198.111: Undo revision 98439 by 5.38.11.244 (talk) undo removal of Globalfoundries 12nm</p>
<hr />
<div>{{amd title|Zen 3|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Zen 3<br />
|designer=AMD<br />
|manufacturer=TSMC<br />
|manufacturer 2=GlobalFoundries<br />
|introduction=October 8, 2020<br />
|process=7nm<br />
|process 2=12 nm<br />
|type=Superscalar<br />
|oooe=Yes<br />
|speculative=Yes<br />
|renaming=Yes<br />
|stages=19<br />
|decode=4-way<br />
|isa=x86-64<br />
|extension=MOVBE<br />
|extension 2=MMX<br />
|extension 3=SSE<br />
|extension 4=SSE2<br />
|extension 5=SSE3<br />
|extension 6=SSSE3<br />
|extension 7=SSE4A<br />
|extension 8=SSE4.1<br />
|extension 9=SSE4.2<br />
|extension 10=POPCNT<br />
|extension 11=AVX<br />
|extension 12=AVX2<br />
|extension 13=AES<br />
|extension 14=PCLMUL<br />
|extension 15=FSGSBASE<br />
|extension 16=RDRND<br />
|extension 17=FMA3<br />
|extension 18=F16C<br />
|extension 19=BMI<br />
|extension 20=BMI2<br />
|extension 21=RDSEED<br />
|extension 22=ADCX<br />
|extension 23=PREFETCHW<br />
|extension 24=CLFLUSHOPT<br />
|extension 25=XSAVE<br />
|extension 26=SHA<br />
|extension 27=UMIP<br />
|extension 28=CLZERO<br />
|predecessor=Zen 2<br />
|predecessor link=amd/microarchitectures/zen 2<br />
|successor=Zen 4<br />
|successor link=amd/microarchitectures/zen 4<br />
}}<br />
'''Zen 3''' is a [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|Zen 2}}. It was publicly released on October 8, 2020. Mainstream Desktop processors hit shelves on November 5, 2020.<br />
<br />
== History ==<br />
[[File:amd zen future roadmap.jpg|400px|right]]<br />
Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize [[7nm+ process]].<br />
<br />
== Codenames ==<br />
[[File:amd zen2-3 roadmap.png|400px|right]]<br />
{{future information}}<br />
<br />
{| class="wikitable"<br />
|-<br />
! Core !! C/T !! Target<br />
|-<br />
| {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]]<br />
|-<br />
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors<br />
|-<br />
| {{amd|Vermeer|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors<br />
|-<br />
| {{amd|Cezanne|l=core}} || Up to 8/16 || Mainstream desktop & mobile processors with GPU <br />
|}<br />
<br />
== Process technology ==<br />
Zen 3 will be fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]], the same process used in Zen 2 Refresh processors. <br />
<br />
== Architecture ==<br />
<br />
There is very limited information available about the architectural improvements of Zen 3.<br />
<br />
=== Key changes from {{\\|Zen 2}} ===<br />
<br />
* +19% IPC<br />
* Unified 8-core CCX with 32 MiB L3$ available to all 8 cores equally. Latency increased by roughly 7 cycles (18%) to an average of 46 cycles.<br />
* Integer unit:<br />
** Integer physical register file increased from 180 to 192 entries<br />
** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.<br />
** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.<br />
** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.<br />
** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.<br />
* Floating point unit:<br />
** FMA latency reduced by 1 cycle from 5 to 4.<br />
** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.<br />
** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.<br />
** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout.<br />
** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.<br />
* Load/store:<br />
** Load throughput increased from 2 to 3, if not 256b.<br />
** Store throughput increased from 1 to 2, if not 256b.<br />
** Store queue increase from 48 to 64 slots.<br />
** Page table walkers tripled from 2 to 6 for TLB miss handling.<br />
* Improved prefetching<br />
* Increased branch prediction bandwidth<br />
** "zero-bubble" branch prediction<br />
** L1 BTB doubled from 512 to 1024 entries<br />
* Improved µop cache<br />
{{expand list}}<br />
<br />
== All Zen 3 Chips ==<br />
<br />
<!-- NOTE: <br />
This table is generated automatically from the data in the actual articles.<br />
If a microprocessor is missing from the list, an appropriate article for it needs to be<br />
created and tagged accordingly.<br />
<br />
Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips<br />
--><br />
{{comp table start}}<br />
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19"><br />
{{comp table header|main|20:List of all Zen 3-based Processors}}<br />
{{comp table header|main|12:Processor|4:Features}}<br />
{{comp table header|cols|Price|Process|Launched|Family|Core|C|T|TDP|L3|Base|Turbo|Max Mem|SMT|SEV|SME|TSME}}<br />
{{comp table header|lsep|25:[[Uniprocessors]]}}<br />
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::1]]<br />
|?full page name<br />
|?model number<br />
|?release price<br />
|?process<br />
|?first launched<br />
|?microprocessor family<br />
|?core name<br />
|?core count<br />
|?thread count<br />
|?tdp<br />
|?l3$ size<br />
|?base frequency#GHz<br />
|?turbo frequency#GHz<br />
|?max memory#GiB<br />
|?has simultaneous multithreading<br />
|?has amd secure encrypted virtualization technology<br />
|?has amd secure memory encryption technology<br />
|?has amd transparent secure memory encryption technology<br />
|format=template<br />
|template=proc table 3<br />
|userparam=18:15<br />
|mainlabel=-<br />
|valuesep=,<br />
|limit=100<br />
}}<br />
{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}<br />
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::>>1]]<br />
|?full page name<br />
|?model number<br />
|?release price<br />
|?process<br />
|?first launched<br />
|?microprocessor family<br />
|?core name<br />
|?core count<br />
|?thread count<br />
|?tdp<br />
|?l3$ size<br />
|?base frequency#GHz<br />
|?turbo frequency#GHz<br />
|?max memory#GiB<br />
|?has simultaneous multithreading<br />
|?has amd secure encrypted virtualization technology<br />
|?has amd secure memory encryption technology<br />
|?has amd transparent secure memory encryption technology<br />
|format=template<br />
|template=proc table 3<br />
|userparam=18:15<br />
|mainlabel=-<br />
|valuesep=,<br />
|limit=100<br />
}}<br />
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]]}}<br />
</table><br />
{{comp table end}}<br />
<br />
== Designers ==<br />
* Mark Evers, Chief Architect<br />
<br />
== Bibliography ==<br />
* AMD 'Tech Day', February 22, 2017<br />
* AMD 2017 Financial Analyst Day, May 16, 2017<br />
<br />
== See Also ==<br />
* AMD {{\\|Zen}}<br />
* Intel {{intel|Tigerlake|l=arch}}<br />
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]</div>
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