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2024-03-28T08:46:48Z
User contributions
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https://en.wikichip.org/w/index.php?title=intel/microarchitectures/gracemont&diff=97718
intel/microarchitectures/gracemont
2020-08-09T10:29:05Z
<p>115.134.19.132: https://videocardz.com/newz/intel-grand-ridge-features-up-to-24-atom-cores-supports-ddr5-and-pcie-4-0 https://cdn.videocardz.com/1/2020/08/Intel-Grand-Ridge-Series.jpg</p>
<hr />
<div>{{intel title|Gracemont|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Gracemont<br />
|designer=Intel<br />
|manufacturer=Intel<br />
|introduction=2021<br />
|process=10 nm<br />
|type=Superscalar<br />
|oooe=Yes<br />
|speculative=Yes<br />
|renaming=Yes<br />
|isa=x86-64<br />
|extension=MOVBE<br />
|extension 2=MMX<br />
|extension 3=SSE<br />
|extension 4=SSE2<br />
|extension 5=SSE3<br />
|extension 6=SSSE3<br />
|extension 7=SSE4.1<br />
|extension 8=SSE4.2<br />
|extension 9=POPCNT<br />
|extension 10=AES<br />
|extension 11=PCLMUL<br />
|extension 12=RDRND<br />
|extension 13=XSAVE<br />
|extension 14=XSAVEOPT<br />
|extension 15=FSGSBASE<br />
|extension 16=PTWRITE<br />
|extension 17=RDPID<br />
|extension 18=SGX<br />
|extension 19=UMIP<br />
|extension 20=GFNI-SSE<br />
|extension 21=CLWB<br />
|extension 22=ENCLV<br />
|extension 23=SHA<br />
|core name=<br />
|core name 2=<br />
|core name 3=<br />
|predecessor=Tremont<br />
|predecessor link=intel/microarchitectures/tremont<br />
}}<br />
'''Gracemont''' is [[Intel]]'s successor to {{\\|Tremont}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.<br />
<br />
== Codenames ==<br />
{| class="wikitable"<br />
! Platform !! Core Name || PCH<br />
|-<br />
| || {{intel|Grand Ridge |l=core}} ||<br />
|}<br />
<br />
== Process Technology ==<br />
Gracemont is designed to take advantage of Intel's [[10 nm process]].<br />
<br />
== Architecture ==<br />
=== Key changes from {{\\|Tremont}}===<br />
{{future information}}<br />
* Core<br />
** Larger Level 1 instruction cache - 64KB per core from 32KB per core<br />
* Memory<br />
** DDR5 (from DDR4)<br />
* I/O<br />
** PCIe 4.0 (from 3.0)</div>
115.134.19.132
https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tiger_lake&diff=97709
intel/microarchitectures/tiger lake
2020-08-05T21:54:51Z
<p>115.134.19.132: https://www.intc.com/investor-relations/events-and-presentations/events-calendar/event-details/2020/Tiger-Lake-Launch/default.aspx "Tiger Lake Virtual Launch Event September 2, 2020"</p>
<hr />
<div>{{intel title|Tiger Lake|arch}}<br />
{{microarchitecture<br />
|atype=CPU<br />
|name=Tiger Lake<br />
|designer=Intel<br />
|manufacturer=Intel<br />
|introduction=September 2, 2020<br />
|process=10 nm<br />
|isa=x86-64<br />
|predecessor=Ice Lake (client)<br />
|predecessor link=intel/microarchitectures/ice lake (client)<br />
|successor=Alder Lake<br />
|successor link=intel/microarchitectures/alder lake<br />
|contemporary=Sapphire Rapids<br />
|contemporary link=intel/microarchitectures/sapphire rapids<br />
|succession=Yes<br />
}}<br />
'''Tiger Lake''' ('''TGL''') is [[Intel]]'s successor to {{\\|Ice Lake (client)|Ice Lake}}, a [[10 nm process|10nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices.<br />
<br />
== Process Technology==<br />
{{main|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}}<br />
Tiger Lake will be manufactured on Intel's third generation enhanced [[10 nm process|10nm++ process]].<br />
<br />
== History ==<br />
[[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]]<br />
Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.<br />
<br />
== Architecture ==<br />
Not much is known about Tiger Lake's architecture.<br />
<br />
=== Key changes from {{\\|Ice Lake}}===<br />
* Core<br />
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}<br />
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core<br />
** 2,25x larger Level 2 cache - 1,25MB per core from 512KB per core<br />
* GPU<br />
** {{intel|Gen11|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe)<br />
** 1.5x more EUs (96, up from 64)<br />
* Display<br />
** [[HDMI]] 2.1 (from HDMI 2.0b)<br />
* I/O<br />
** PCIe 4.0 (from 3.0)<br />
* Hardware Telemetry<br />
** Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.</div>
115.134.19.132